On Tue, Feb 22, 2022 at 10:19:37AM -0800, Anusha Srivatsa wrote:
DG1 at a state where we can safely remove require_force_probe.
BAT is not passing to consider this:
https://intel-gfx-ci.01.org/tree/drm-tip/bat-dg1-5.html
https://intel-gfx-ci.01.org/tree/drm-tip/bat-dg1-6.html
<6> [619.626490] i915 0000:03:00.0: [drm] Got error capture: status = 0
<3> [619.626495] i915 0000:03:00.0: [drm] *ERROR* GuC engine reset request failed on 2:0 (vecs0) because 0x00000000
<6> [619.772548] i915 0000:03:00.0: [drm] GPU HANG: ecode 12:0:00000000
<5> [619.777166] i915 0000:03:00.0: [drm] Resetting chip for GuC failed to reset engine mask=0x400
<6> [619.781956] i915 0000:03:00.0: [drm] GuC firmware i915/dg1_guc_69.0.3.bin version 69.0
<6> [619.781960] i915 0000:03:00.0: [drm] HuC firmware i915/dg1_huc_7.9.3.bin version 7.9
<7> [619.800021] i915 0000:03:00.0: [drm:guc_enable_communication [i915]] GuC communication enabled
<6> [619.803067] i915 0000:03:00.0: [drm] HuC authenticated
<6> [619.807778] i915 0000:03:00.0: [drm] GuC submission enabled
<6> [619.807780] i915 0000:03:00.0: [drm] GuC SLPC enabled
<6> [619.848454] i915 0000:03:00.0: [drm] Got error capture: status = 0
<6> [620.617459] i915 0000:03:00.0: [drm] GPU HANG: ecode 12:0:00000000
<6> [620.621833] i915_reset_engine(vecs0:others-priority): 2 resets
<3> [620.655812] Global reset (count=1)!
<3> [620.724265] i915/intel_hangcheck_live_selftests: igt_reset_engines failed with error -22
Lucas De Marchi
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f449c454b6f8..cafc569fdf66 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -909,7 +909,6 @@ static const struct intel_device_info dg1_info = {
.graphics.rel = 10,
PLATFORM(INTEL_DG1),
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
- .require_force_probe = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
BIT(VCS0) | BIT(VCS2),
--
2.25.1
