✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915: Fix for PHY_MISC_TC1 offset

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Title: Project List - Patchwork
Patch Details
Series:series starting with [CI,1/3] drm/i915: Fix for PHY_MISC_TC1 offset
URL:https://patchwork.freedesktop.org/series/100373/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/index.html

CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22326

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/index.html

Participating hosts (44 -> 41)

Additional (1): fi-kbl-8809g
Missing (4): fi-bsw-cyan bat-jsl-2 fi-bdw-5557u shard-tglu

Known issues

Here are the changes found in Patchwork_22326 that come from known issues:

IGT changes

Issues hit

Possible fixes

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes

CI-20190529: 20190529
CI_DRM_11244: 6bde77454434bcd6c80f64fc638ffd0c8e1d5b07 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6347: 37ea4c86f97c0e05fcb6b04cff72ec927930536e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22326: f128d3a75f3deaa77d48c7c146c4849d61d95c64 @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

f128d3a75f3d drm/i915/dg2: Enable 5th port
d20e83eacf5a drm/i915/dg2: Drop 38.4 MHz MPLLB tables
2bc5a2246dec drm/i915: Fix for PHY_MISC_TC1 offset


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