On Wed, Feb 16, 2022 at 11:54:00AM +0200, Jani Nikula wrote:
> On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > snb_wm_latency_quirk() already boosts up the latency values
> > so the extra warning about the SSKPD value being insufficient
> > is now redundant. Drop it.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> I just might not understand what's going on...
>
> ...but snb_wm_latency_quirk() is only called for display 6, not for ivb
> where the check is also removed?
Hmm. Not sure this was ever an issue on IVB. I think the BIOSen
might have gotten all fixed by that time. Not sure. I guess we can
keep this for now. And maybe I should just rewrite to look at the
parsed latency values instead...
>
> BR,
> Jani.
>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 15 ---------------
> > 1 file changed, 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 0fa3dce9bd54..34e46a9b8300 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -7432,17 +7432,6 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
> > }
> > }
> >
> > -static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
> > -{
> > - u32 tmp;
> > -
> > - tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);
> > - if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
> > - drm_dbg_kms(&dev_priv->drm,
> > - "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
> > - tmp);
> > -}
> > -
> > static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> > {
> > u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> > @@ -7500,8 +7489,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> > g4x_disable_trickle_feed(dev_priv);
> >
> > cpt_init_clock_gating(dev_priv);
> > -
> > - gen6_check_mch_setup(dev_priv);
> > }
> >
> > static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
> > @@ -7853,8 +7840,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
> >
> > if (!HAS_PCH_NOP(dev_priv))
> > cpt_init_clock_gating(dev_priv);
> > -
> > - gen6_check_mch_setup(dev_priv);
> > }
> >
> > static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Ville Syrjälä
Intel
