On Tue, Feb 08, 2022 at 09:11:40PM -0800, Matt Roper wrote:
> The random order of register definitions we have today causes a lot of
> confusion and unintentional duplication when new registers/bits are
> added to the driver. Let's order the GT register file by MMIO offset
>
> A couple duplicated/unused register definitions are dropped while doing
> this re-order: GEN11_GT_INTR_DW{0,1}, GEN11_IIR_REG{0,1}_SELECTOR, and
> GEN11_INTR_IDENTITY_REG{0,1} aren't used anywhere in the driver because
> we have other parameterized macros referencing those registers.
>
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2289 ++++++++++++-----------
> 1 file changed, 1147 insertions(+), 1142 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 3b1cae766741..e48a2ffed4fd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -8,67 +8,95 @@
>
> #include "i915_reg_defs.h"
>
> -#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
Drive by comment: This seems a bit misplaced in intel_gt_regs.h.
I'm thinking we probably want a intel_mchbar_regs.h for these.
--
Ville Syrjälä
Intel
