On Fri, 12 Nov 2021, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Use REG_GENMASK() & co. when dealing with PIPESRC.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_display.c | 7 ++++---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 3 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 2194f74101ae..f586e39cb378 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -1048,8 +1048,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
> plane_config->base = base;
>
> val = intel_de_read(dev_priv, PIPESRC(pipe));
> - fb->width = ((val >> 16) & 0xfff) + 1;
> - fb->height = ((val >> 0) & 0xfff) + 1;
I guess the mask width change is worth noting in the commit message.
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> + fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
> + fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
>
> val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
> fb->pitches[0] = val & 0xffffffc0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4e29032b29d6..e1959a17805c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3236,7 +3236,8 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
> * always be the user's requested size.
> */
> intel_de_write(dev_priv, PIPESRC(pipe),
> - ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
> + PIPESRC_WIDTH(crtc_state->pipe_src_w - 1) |
> + PIPESRC_HEIGHT(crtc_state->pipe_src_h - 1));
> }
>
> static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
> @@ -3307,8 +3308,8 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
> u32 tmp;
>
> tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
> - pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
> - pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
> + pipe_config->pipe_src_w = REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1;
> + pipe_config->pipe_src_h = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1;
> }
>
> static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eea009e76e15..211e2b415e50 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4476,6 +4476,10 @@ enum {
> #define _VSYNC_A 0x60014
> #define _EXITLINE_A 0x60018
> #define _PIPEASRC 0x6001c
> +#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
> +#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
> +#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
> +#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
> #define _BCLRPAT_A 0x60020
> #define _VSYNCSHIFT_A 0x60028
> #define _PIPE_MULT_A 0x6002c
--
Jani Nikula, Intel Open Source Graphics Center
