Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/i915_reg.h
between commit:
77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to pmu")
from Linus' tree and commit:
202b1f4c1234 ("drm/i915/gt: Move engine registers to their own header")
from the drm-intel tree.
I fixed it up (see below - maybe should be done better?) and can carry the
fix as necessary. This is now fixed as far as linux-next is concerned,
but any non trivial conflicts should be mentioned to your upstream
maintainer when your tree is submitted for merging. You may also want
to consider cooperating with the maintainer of the conflicting tree to
minimise any particularly complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/i915/i915_reg.h
index 971d601fe751,cf168c3e0471..000000000000
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@@ -2661,52 -1825,7 +1843,9 @@@
#define AUX_INV REG_BIT(0)
#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
- #define RING_ACTHD(base) _MMIO((base) + 0x74)
- #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
- #define RING_NOPID(base) _MMIO((base) + 0x94)
- #define RING_IMR(base) _MMIO((base) + 0xa8)
- #define RING_HWSTAM(base) _MMIO((base) + 0x98)
- #define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
- #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
- #define TAIL_ADDR 0x001FFFF8
- #define HEAD_WRAP_COUNT 0xFFE00000
- #define HEAD_WRAP_ONE 0x00200000
- #define HEAD_ADDR 0x001FFFFC
- #define RING_NR_PAGES 0x001FF000
- #define RING_REPORT_MASK 0x00000006
- #define RING_REPORT_64K 0x00000002
- #define RING_REPORT_128K 0x00000004
- #define RING_NO_REPORT 0x00000000
- #define RING_VALID_MASK 0x00000001
- #define RING_VALID 0x00000001
- #define RING_INVALID 0x00000000
- #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
- #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
- #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
+#define GUCPMTIMESTAMP _MMIO(0xC3E8)
+
- /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
- #define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
- #define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
-
- #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
- #define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
- #define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
- #define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
- #define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
- #define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
- #define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
- #define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
- #define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
- #define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
- #define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
- #define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
- #define RING_FORCE_TO_NONPRIV_MASK_VALID \
- (RING_FORCE_TO_NONPRIV_RANGE_MASK \
- | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
- #define RING_MAX_NONPRIV_SLOTS 12
-
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
@@@ -2778,27 -1885,7 +1905,10 @@@
#define GEN2_INSTDONE _MMIO(0x2090)
#define NOPID _MMIO(0x2094)
#define HWSTAM _MMIO(0x2098)
- #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
- #define RING_BBSTATE(base) _MMIO((base) + 0x110)
- #define RING_BB_PPGTT (1 << 5)
- #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
- #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
- #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
- #define RING_BBADDR(base) _MMIO((base) + 0x140)
- #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
- #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
- #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
- #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
- #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
-
- #define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
- #define IECPUNIT_CLKGATE_DIS REG_BIT(22)
+#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
+#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
+
#define ERROR_GEN6 _MMIO(0x40a0)
#define GEN7_ERR_INT _MMIO(0x44040)
#define ERR_INT_POISON (1 << 31)
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