On Wed, 12 Jan 2022, Matt Roper <matthew.d.roper@xxxxxxxxx> wrote: > On Wed, Jan 12, 2022 at 05:09:55PM +0200, Ville Syrjälä wrote: >> On Mon, Jan 10, 2022 at 09:15:52PM -0800, Matt Roper wrote: >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> > index 3ef332833c4c..a4c9d2005c46 100644 >> > --- a/drivers/gpu/drm/i915/i915_reg.h >> > +++ b/drivers/gpu/drm/i915/i915_reg.h >> > @@ -2858,10 +2858,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) >> > #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ >> > #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) >> > #define GFX_FLSH_CNTL_EN (1 << 0) >> > -#define ECOSKPD _MMIO(0x21d0) >> > -#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) >> > -#define ECO_GATING_CX_ONLY (1 << 3) >> > -#define ECO_FLIP_DONE (1 << 0) >> > +#define ECOSKPD(base) _MMIO((base) + 0x1d0) >> > +#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) >> > +#define ECO_GATING_CX_ONLY REG_BIT(3) >> > +#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3) >> > +#define ECO_FLIP_DONE REG_BIT(0) >> > +#define GEN6_BLITTER_LOCK_SHIFT 16 >> >> This looks messy. The register contents are (mostly?) unique for >> each engine, so this is making it rather hard to see which register >> takes which bits. I think we should at least group the bits clearly >> based on which engine they belong to. > > Makes sense. I'll send a follow-up patch tomorrow that reorganizes this > a bit. For things that you're rearranging in the series, sure, please clean it up. But for stuff already in i915_reg.h, let's not let those block this work. Split up the file, and IMO the cleanup will be easier in the smaller files with follow-up patches. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center
