Rather than having separate definitions for each engine, create a single
parameterized macro that takes the engine base offset. This will also
ensure we get to the proper offset if we ever need to use these
registers on newer platforms (where the media engine offsets have
changed).
Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 8 ++++----
drivers/gpu/drm/i915/i915_reg.h | 6 +-----
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index c3155ee58689..45891e6f0b98 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -449,10 +449,10 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
enable_rc6 = false;
}
- if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
+ if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
drm_dbg(&i915->drm,
"Engine Idle wait time not set properly.\n");
enable_rc6 = false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86e459010465..23330faecf07 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9297,11 +9297,7 @@ enum {
#define RC6_CTX_IN_DRAM (1 << 0)
#define RC6_CTX_BASE _MMIO(0xD48)
#define RC6_CTX_BASE_MASK 0xFFFFFFF0
-#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
-#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
-#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
-#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
-#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
+#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
#define IDLE_TIME_MASK 0xFFFFF
#define FORCEWAKE _MMIO(0xA18C)
#define FORCEWAKE_VLV _MMIO(0x1300b0)
--
2.34.1
