+ } else if (gen >= 4) {
+ batch[++i] = 0;
+ batch[++i] = delta;
+ reloc.offset += sizeof(uint32_t);
+ } else {
+ batch[i]--;
+ batch[++i] = delta;
+ }
+ batch[++i] = target_value;
+ batch[++i] = MI_BATCH_BUFFER_END;
+ gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, obj[BATCH].handle);
+ put_offset(ahnd, obj[BATCH].handle);
+}
diff --git a/lib/igt_store.h b/lib/igt_store.h
new file mode 100644
index 000000000..4d5979e07
--- /dev/null
+++ b/lib/igt_store.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt_gt.h"
+
+void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ int fence, uint32_t target_handle,
+ uint64_t target_offset, uint32_t target_value);
diff --git a/lib/meson.build b/lib/meson.build
index b9568a71b..3e43316d1 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -72,6 +72,7 @@ lib_sources = [
'igt_map.c',
'igt_pm.c',
'igt_dummyload.c',
+ 'igt_store.c',
'uwildmat/uwildmat.c',
'igt_kmod.c',
'igt_panfrost.c',
diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index 9a6336ce9..c4091a454 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -28,6 +28,7 @@
#include "i915/gem.h"
#include "i915/gem_create.h"
#include "igt.h"
+#include "igt_store.h"
#include "igt_syncobj.h"
#include "igt_sysfs.h"
#include "igt_vgem.h"
@@ -57,74 +58,6 @@ struct sync_merge_data {
#define MI_SEMAPHORE_SAD_EQ_SDD (4 << 12)
#define MI_SEMAPHORE_SAD_NEQ_SDD (5 << 12)
-static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e,
- int fence, uint32_t target, uint64_t target_offset,
- unsigned offset_value)
-{
- const int SCRATCH = 0;
- const int BATCH = 1;
- const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
- struct drm_i915_gem_exec_object2 obj[2];
- struct drm_i915_gem_relocation_entry reloc;
- struct drm_i915_gem_execbuffer2 execbuf;
- uint32_t batch[16], delta;
- uint64_t bb_offset;
- int i;
-
- memset(&execbuf, 0, sizeof(execbuf));
- execbuf.buffers_ptr = to_user_pointer(obj);
- execbuf.buffer_count = 2;
- execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
- execbuf.rsvd1 = ctx->id;
- execbuf.rsvd2 = fence;
- if (gen < 6)
- execbuf.flags |= I915_EXEC_SECURE;
-
- memset(obj, 0, sizeof(obj));
- obj[SCRATCH].handle = target;
-
- obj[BATCH].handle = gem_create(fd, 4096);
- obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
- obj[BATCH].relocation_count = !ahnd ? 1 : 0;
- bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
- memset(&reloc, 0, sizeof(reloc));
-
- i = 0;
- delta = sizeof(uint32_t) * offset_value;
- if (!ahnd) {
- reloc.target_handle = obj[SCRATCH].handle;
- reloc.presumed_offset = -1;
- reloc.offset = sizeof(uint32_t) * (i + 1);
- reloc.delta = delta;
- reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
- reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
- } else {
- obj[SCRATCH].offset = target_offset;
- obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
- obj[BATCH].offset = bb_offset;
- obj[BATCH].flags |= EXEC_OBJECT_PINNED;
- }
- batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
- if (gen >= 8) {
- batch[++i] = target_offset + delta;
- batch[++i] = target_offset >> 32;
- } else if (gen >= 4) {
- batch[++i] = 0;
- batch[++i] = delta;
- reloc.offset += sizeof(uint32_t);
- } else {
- batch[i]--;
- batch[++i] = delta;
- }
- batch[++i] = offset_value;
- batch[++i] = MI_BATCH_BUFFER_END;
- gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
- gem_execbuf(fd, &execbuf);
- gem_close(fd, obj[BATCH].handle);
- put_offset(ahnd, obj[BATCH].handle);
-}
-
static bool fence_busy(int fence)
{
return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
@@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
continue;
if (flags & NONBLOCK) {
- store(fd, ahnd, ctx, e2, spin->out_fence,
- scratch, scratch_offset, i);
+ igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
+ scratch, scratch_offset, i);
} else {
igt_fork(child, 1) {
ahnd = get_reloc_ahnd(fd, ctx->id);
- store(fd, ahnd, ctx, e2, spin->out_fence,
- scratch, scratch_offset, i);
+ igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
+ scratch, scratch_offset, i);
put_ahnd(ahnd);
}
}
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 20653b479..4cb9b8b85 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -36,6 +36,7 @@
#include "i915/gem.h"
#include "i915/gem_create.h"
#include "igt.h"
+#include "igt_store.h"
#include "igt_sysfs.h"
#include "igt_debugfs.h"
#include "sw_sync.h"
@@ -51,64 +52,6 @@ static int sysfs = -1;
IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
-/* Requires master for STORE_DWORD on gen4/5 */
-static void store(int fd, const struct intel_execution_engine2 *e,
- int fence, uint32_t target, unsigned offset_value)
-{
- const int SCRATCH = 0;
- const int BATCH = 1;
- const int gen = intel_gen(intel_get_drm_devid(fd));
- struct drm_i915_gem_exec_object2 obj[2];
- struct drm_i915_gem_relocation_entry reloc;
- struct drm_i915_gem_execbuffer2 execbuf;
- uint32_t batch[16];
- int i;
-
- memset(&execbuf, 0, sizeof(execbuf));
- execbuf.buffers_ptr = to_user_pointer(obj);
- execbuf.buffer_count = ARRAY_SIZE(obj);
- execbuf.flags = e->flags;
- if (fence != -1) {
- execbuf.flags |= I915_EXEC_FENCE_IN;
- execbuf.rsvd2 = fence;
- }
- if (gen < 6)
- execbuf.flags |= I915_EXEC_SECURE;
-
- memset(obj, 0, sizeof(obj));
- obj[SCRATCH].handle = target;
-
- obj[BATCH].handle = gem_create(fd, 4096);
- obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
- obj[BATCH].relocation_count = 1;
- memset(&reloc, 0, sizeof(reloc));
-
- i = 0;
- reloc.target_handle = obj[SCRATCH].handle;
- reloc.presumed_offset = -1;
- reloc.offset = sizeof(uint32_t) * (i + 1);
- reloc.delta = sizeof(uint32_t) * offset_value;
- reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
- reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
- batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
- if (gen >= 8) {
- batch[++i] = reloc.delta;
- batch[++i] = 0;
- } else if (gen >= 4) {
- batch[++i] = 0;
- batch[++i] = reloc.delta;
- reloc.offset += sizeof(uint32_t);
- } else {
- batch[i]--;
- batch[++i] = reloc.delta;
- }
- batch[++i] = offset_value;
- batch[++i] = MI_BATCH_BUFFER_END;
- gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
- gem_execbuf(fd, &execbuf);
- gem_close(fd, obj[BATCH].handle);
-}
-
static void check_alive(void)
{
const struct intel_execution_engine2 *engine;
@@ -138,7 +81,7 @@ static void check_alive(void)
continue;
/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
- store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
+ igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
i++;
}
--
2.25.1
