On Thu, 02 Dec 2021, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> On Thu, Dec 02, 2021 at 04:44:56PM +0200, Jani Nikula wrote:
>> The mode set sequence for 128b/132b requires setting the div32 version
>> of MPLLB clock.
>>
>> Bspec: 53880, 54128
>
> Weird place for that information when all the other bits are listed
> in the clock programming section :/
>
>> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Thanks, pushed.
>
>> ---
>> drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 ++
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> 2 files changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> index c2251218a39e..09f405e4d363 100644
>> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> @@ -186,6 +186,7 @@ static const struct intel_mpllb_state dg2_dp_uhbr10_100 = {
>> REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
>> REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
>> REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
>> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
>> REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
>> .mpllb_div2 =
>> REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
>> @@ -369,6 +370,7 @@ static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = {
>> REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
>> REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
>> REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
>> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
>> REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
>> .mpllb_div2 =
>> REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 3450818802c2..1fad1d593e13 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2265,6 +2265,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>> #define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
>> #define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
>> #define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
>> +#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
>>
>> #define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
>> #define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
>> --
>> 2.30.2
--
Jani Nikula, Intel Open Source Graphics Center
