On Fri, Nov 19, 2021 at 03:13:44PM +0200, Mika Kahola wrote:
> For CD clock squashing method, we need to define corresponding CD clock table for
> reference clocks, dividers and ratios for all CD clock options.
>
> BSpec: 54034
>
> v2: Add CD squashing waveforms as part of CD clock table (Ville)
> v3: Waveform is 16 bits wide (Ville)
> [v4: vsyrjala: Nuke the non-squasher based table,
> Set .divider=2 for consistency,
> Pack intel_cdclk_vals a bit nicer]
> v5: Fix error in waveform value (Swati)
> v6 (Lucas): Rebase on upstream
> v7 (MattR): Drop 40.8, 81.6, and 122.4 MHz frequencies to reflect new
> bspec update.
>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> Signed-off-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++++++++++++------
> drivers/gpu/drm/i915/display/intel_cdclk.h | 1 +
> 2 files changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 91c19e0a98d7..7af4cb965060 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1313,12 +1313,19 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> };
>
> static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
> - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> - { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> + { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> + { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> + { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
> + { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
> + { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
> + { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
> + { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
> + { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
> + { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
> + { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
> + { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> {}
> };
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 309b3f394e24..89ca59c46102 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -19,6 +19,7 @@ struct intel_crtc_state;
> struct intel_cdclk_vals {
> u32 cdclk;
> u16 refclk;
> + u16 waveform;
> u8 divider; /* CD2X divider * 2 */
> u8 ratio;
> };
> --
> 2.27.0
>
