On Mon, Nov 08, 2021 at 04:26:44PM -0800, Michael Cheng wrote:
Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
(Some architectures don't even have these macros defined, like ARM64).
Instead of re-using bits defined for the CPU, we should use bits
defined for i915. This patch introduces two new macros,
I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
Looking at the bspecs for pre gen 12 and gen 12, bit 0 and 1 are the
same throughout the generations.
Signed-off-by: Michael Cheng <michael.cheng@xxxxxxxxx>
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++
drivers/gpu/drm/i915/gvt/gtt.c | 12 ++++++------
4 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 9966e9dc5218..f89b50ffc286 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -18,7 +18,7 @@
static u64 gen8_pde_encode(const dma_addr_t addr,
const enum i915_cache_level level)
{
- u64 pde = addr | _PAGE_PRESENT | _PAGE_RW;
+ u64 pde = addr | I915_PAGE_PRESENT | I915_PAGE_RW;
if (level != I915_CACHE_NONE)
pde |= PPAT_CACHED_PDE;
@@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
+ gen8_pte_t pte = addr | I915_PAGE_PRESENT | I915_PAGE_RW;
if (unlikely(flags & PTE_READ_ONLY))
- pte &= ~_PAGE_RW;
+ pte &= ~I915_PAGE_RW;
if (flags & PTE_LM)
pte |= GEN12_PPGTT_PTE_LM;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 1fb4a03d7ac3..3f8e1ee0fbfa 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -207,7 +207,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- gen8_pte_t pte = addr | _PAGE_PRESENT;
+ gen8_pte_t pte = addr | I915_PAGE_PRESENT;
if (flags & PTE_LM)
pte |= GEN12_GGTT_PTE_LM;
GEN12_GGTT_PTE_LM is also bit 1 though.
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index dfeaef680aac..fba9c0c18f4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -39,6 +39,9 @@
#define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
+#define I915_PAGE_PRESENT BIT_ULL(0)
+#define I915_PAGE_RW BIT_ULL(1)
I will leave it for others to comment, but this may be confusing as this
is only valid for ppgtt, not ggtt. On ggtt, at least on graphics_ver ==
12 the only bit is bit 0, meaning page present. Bit 1, as commented
above is the LM flag for the platforms that have that.
If we are going with a single value for VALID/PRESENT, we may also want
to get rid of GEN6_PTE_VALID and GEN6_PDE_VALID
And for ggtt, maybe also get rid of BYT_PTE_WRITEABLE
Adding some more people who touched these files for feedback.
thanks
Lucas De Marchi
