On Mon, Oct 18, 2021 at 02:50:27PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Chop i9xx_plane_update() into two halves. Fist half becomes
> the _noarm() variant, second part the _arm() variant.
>
> Fortunately I have already previously grouped the register
> writes into roughtly the correct order, so the split looks
> surprisingly clean.
>
> One slightly surprising fact was that the CHV pipe B PRIMPOS/SIZE
> registers are self arming unlike their pre-ctg DSPPOS/SIZE
> counterparts. In fact all the new CHV pipe B registers are
> self arming.
>
> I didn't do any i915_update_info measurements for this one
> alone. I'll get total numbers with the corrsponding sprite
> plane changes.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 61 +++++++++++++++--------
> 1 file changed, 40 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 93163f9100a8..9dfd0a53e0ee 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -418,23 +418,49 @@ static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
> return DIV_ROUND_UP(pixel_rate * num, den);
> }
>
> -/* TODO: split into noarm+arm pair */
> +static void i9xx_plane_update_noarm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> + unsigned long irqflags;
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> + intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
> + plane_state->view.color_plane[0].stride);
> +
> + if (DISPLAY_VER(dev_priv) < 4) {
> + int crtc_x = plane_state->uapi.dst.x1;
> + int crtc_y = plane_state->uapi.dst.y1;
> + int crtc_w = drm_rect_width(&plane_state->uapi.dst);
> + int crtc_h = drm_rect_height(&plane_state->uapi.dst);
> +
> + /*
> + * PLANE_A doesn't actually have a full window
> + * generator but let's assume we still need to
> + * program whatever is there.
> + */
> + intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
> + (crtc_y << 16) | crtc_x);
> + intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
> + ((crtc_h - 1) << 16) | (crtc_w - 1));
> + }
> +
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
> static void i9xx_plane_update_arm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> - u32 linear_offset;
> int x = plane_state->view.color_plane[0].x;
> int y = plane_state->view.color_plane[0].y;
> - int crtc_x = plane_state->uapi.dst.x1;
> - int crtc_y = plane_state->uapi.dst.y1;
> - int crtc_w = drm_rect_width(&plane_state->uapi.dst);
> - int crtc_h = drm_rect_height(&plane_state->uapi.dst);
> + u32 dspcntr, dspaddr_offset, linear_offset;
> unsigned long irqflags;
> - u32 dspaddr_offset;
> - u32 dspcntr;
>
> dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
>
> @@ -447,20 +473,12 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> - intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
> - plane_state->view.color_plane[0].stride);
> + if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
> + int crtc_x = plane_state->uapi.dst.x1;
> + int crtc_y = plane_state->uapi.dst.y1;
> + int crtc_w = drm_rect_width(&plane_state->uapi.dst);
> + int crtc_h = drm_rect_height(&plane_state->uapi.dst);
>
> - if (DISPLAY_VER(dev_priv) < 4) {
> - /*
> - * PLANE_A doesn't actually have a full window
> - * generator but let's assume we still need to
> - * program whatever is there.
> - */
> - intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
> - (crtc_y << 16) | crtc_x);
> - intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
> - ((crtc_h - 1) << 16) | (crtc_w - 1));
> - } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
> intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
> (crtc_y << 16) | crtc_x);
> intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
> @@ -852,6 +870,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> plane->max_stride = ilk_primary_max_stride;
> }
>
> + plane->update_noarm = i9xx_plane_update_noarm;
> plane->update_arm = i9xx_plane_update_arm;
> plane->disable_arm = i9xx_plane_disable_arm;
> plane->get_hw_state = i9xx_plane_get_hw_state;
> --
> 2.32.0
>
