On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Prepare for per-lane drive settings by querying the desired vswing
> level per-lane.
Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index 5e20f340730f..c2251218a39e 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -58,7 +58,6 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> const struct intel_ddi_buf_trans *trans;
> enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> - int level = intel_ddi_level(encoder, crtc_state, 0);
> int n_entries, ln;
>
> trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
> @@ -66,6 +65,7 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
> return;
>
> for (ln = 0; ln < 4; ln++) {
> + int level = intel_ddi_level(encoder, crtc_state, ln);
> u32 val = 0;
>
> val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);
