On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Prepare for per-lane drive settings by querying the desired vswing
> level per-lane.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index aa789cabc55b..4c400f0e7347 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1039,7 +1039,6 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - int level = intel_ddi_level(encoder, crtc_state, 0);
> const struct intel_ddi_buf_trans *trans;
> enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> int n_entries, ln;
> @@ -1069,6 +1068,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>
> /* Program PORT_TX_DW2 */
> for (ln = 0; ln < 4; ln++) {
> + int level = intel_ddi_level(encoder, crtc_state, ln);
> +
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy));
> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> RCOMP_SCALAR_MASK);
> @@ -1082,6 +1083,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> /* Program PORT_TX_DW4 */
> /* We cannot write to GRP. It would overwrite individual loadgen. */
> for (ln = 0; ln < 4; ln++) {
> + int level = intel_ddi_level(encoder, crtc_state, ln);
> +
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> CURSOR_COEFF_MASK);
> @@ -1093,6 +1096,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>
> /* Program PORT_TX_DW7 */
> for (ln = 0; ln < 4; ln++) {
> + int level = intel_ddi_level(encoder, crtc_state, ln);
> +
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy));
> val &= ~N_SCALAR_MASK;
> val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
The cover letter or one of the earlier patches should have some explanation about the reasons of this the group to lane conversion.
Reading one of the later patches I understood is because DP 2.0 allows different level per lane but would be nice to know for sure the reason.
What if it is only using 2 lanes? Programming disabled lanes will cause any issue?
