On Thu, Oct 28, 2021 at 04:04:49PM -0700, José Roberto de Souza wrote:
> New workaround added to specification, requiring bit 15 of
> GEN8_CHICKEN_DCPR_1 to be programed before power well 1 is enabled.
>
> BSpec: 54369
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
The spec doesn't require it, so probably not re-enabling clock gating
after disabling PW#1 won't cause a problem somewhere else. But if so
the wa would be better placed in adlp_init_clock_gating().
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 5 +++++
> drivers/gpu/drm/i915/i915_reg.h | 7 ++++---
> 2 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 6637760d24e0c..344e3d6967020 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -435,6 +435,11 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
>
> pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
> SKL_PW_CTL_IDX_TO_PG(pw_idx);
> +
> + /* Wa_16013190616:adlp */
> + if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1)
> + intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC);
> +
> /*
> * For PW1 we have to wait both for the PW0/PG0 fuse state
> * before enabling the power well and PW1/PG1's own fuse
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fd58757e846a6..541c16aee90da 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8310,9 +8310,10 @@ enum {
> #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4)
>
> #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> -#define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
> -#define ICL_DELAY_PMRSP (1 << 22)
> -#define MASK_WAKEMEM (1 << 13)
> +#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
> +#define ICL_DELAY_PMRSP REG_BIT(22)
> +#define DISABLE_FLR_SRC REG_BIT(15)
> +#define MASK_WAKEMEM REG_BIT(13)
>
> #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
> #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
> --
> 2.33.1
>
