On Wed, Oct 06, 2021 at 11:49:37PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Our lane power down defines already include the necessary shift, > don't shit them a second time. > > Fortunately we masked off the correct bits, so we accidentally > left all lanes powered up all the time. > > Bits 8-11 where we end up writing our misdirected lane mask are > documented as MBZ, but looks like you can actually write there > so they're not read only bits. No idea what side effect the > bogus register write might have. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4151 > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_combo_phy.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c > index 634e8d449457..f628e0542933 100644 > --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c > @@ -301,7 +301,7 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, > > val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); > val &= ~PWR_DOWN_LN_MASK; > - val |= lane_mask << PWR_DOWN_LN_SHIFT; > + val |= lane_mask; > intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); > } > > -- > 2.32.0 >
