On Tue, May 21, 2013 at 10:27:53AM -0300, Paulo Zanoni wrote: > 2013/5/21 Daniel Vetter <daniel at ffwll.ch>: > > On Fri, May 03, 2013 at 05:23:45PM -0300, Paulo Zanoni wrote: > >> From: Paulo Zanoni <paulo.r.zanoni at intel.com> > >> > >> Commit 1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a added a workaround > >> inside haswell_init_clock_gating and mentioned it is "a workaround for > >> early silicon revisions and should be removed later". This workaround > >> is documented in bit 31 of PRI_CTL. I asked Arthur and he mentioned > >> that setting FORCE_ARB_IDLE_PLANES replaces that workaround for the > >> newer machines. So use the new one. > >> > >> Also notice that there's still another workaround for PRI_CTL that > >> involves WM_DBG, but it's not the one we're reverting. And notice that > >> we were previously setting WM_DBG_DISALLOW_MULTIPIPE_LP which disables > >> the LP watermarks when more than one pipe is used, and we really don't > >> want this because we need the LP watermarks if we want to reach deeper > >> PC states. > >> > >> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com> > > > > I've applied all the patches in this series safe for the target_clock one. > > But this patch here is missing the w/a tag, can you please supply that one > > in a quick reply so that I can smash it into the patch? > > Just like most display workarounds, this one doesn't have a name. Actually I found a name for it in BSpec: WaRsPkgCStateDisplayPMReq > > > > > Thanks, Daniel > >> --- > >> drivers/gpu/drm/i915/i915_reg.h | 3 +++ > >> drivers/gpu/drm/i915/intel_pm.c | 10 ++-------- > >> 2 files changed, 5 insertions(+), 8 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > >> index aec569f..5879f23 100644 > >> --- a/drivers/gpu/drm/i915/i915_reg.h > >> +++ b/drivers/gpu/drm/i915/i915_reg.h > >> @@ -3697,6 +3697,9 @@ > >> # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) > >> # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) > >> > >> +#define CHICKEN_PAR1_1 0x42080 > >> +#define FORCE_ARB_IDLE_PLANES (1 << 14) > >> + > >> #define DISP_ARB_CTL 0x45000 > >> #define DISP_TILE_SURFACE_SWIZZLING (1<<13) > >> #define DISP_FBC_WM_DIS (1<<15) > >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > >> index b56de92..2297476 100644 > >> --- a/drivers/gpu/drm/i915/intel_pm.c > >> +++ b/drivers/gpu/drm/i915/intel_pm.c > >> @@ -4042,14 +4042,8 @@ static void haswell_init_clock_gating(struct drm_device *dev) > >> /* WaSwitchSolVfFArbitrationPriority */ > >> I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); > >> > >> - /* XXX: This is a workaround for early silicon revisions and should be > >> - * removed later. > >> - */ > >> - I915_WRITE(WM_DBG, > >> - I915_READ(WM_DBG) | > >> - WM_DBG_DISALLOW_MULTIPLE_LP | > >> - WM_DBG_DISALLOW_SPRITE | > >> - WM_DBG_DISALLOW_MAXFIFO); > >> + I915_WRITE(CHICKEN_PAR1_1, > >> + I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); > >> > >> lpt_init_clock_gating(dev); > >> } > >> -- > >> 1.7.10.4 > >> > >> _______________________________________________ > >> Intel-gfx mailing list > >> Intel-gfx at lists.freedesktop.org > >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > > > > -- > Paulo Zanoni > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel OTC
