Re: [PATCH 2/2] drm/i915/dmabuf: drop the flush on discrete

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On 22/10/2021 10:26, Thomas Hellström wrote:
Hi, Matt

On 10/21/21 14:53, Matthew Auld wrote:
We were overzealous here; even though discrete is non-LLC, it should
still be always coherent.

Signed-off-by: Matthew Auld <matthew.auld@xxxxxxxxx>
Cc: Thomas Hellström <thomas.hellstrom@xxxxxxxxxxxxxxx>
---
  drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index a45d0ec2c5b6..848e81368043 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -251,7 +251,8 @@ static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj)
          return PTR_ERR(pages);
      /* XXX: consider doing a vmap flush or something */
-    if (!HAS_LLC(i915) || i915_gem_object_can_bypass_llc(obj))
+    if ((!HAS_LLC(i915) && !IS_DGFX(i915)) ||

Q: I notice that DG1 at least has HAS_SNOOP. Would it be incorrect to use that in this case?

AFAIK DG1 is special in that CACHE_NONE will still snoop transactions, which is not the case for other HAS_SNOOP platforms. AFAIK that is part of the reason why we also just force CACHE_LLC everywhere on DG1.

Could maybe do s/IS_DGFX/IS_DG1/ here? In case that changes on other discrete platforms. And then add a comment.


/Thomas



+        i915_gem_object_can_bypass_llc(obj))
          wbinvd_on_all_cpus();
      sg_page_sizes = i915_sg_dma_sizes(pages->sgl);



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