On Wed, May 22, 2013 at 05:08:06PM +0100, Chris Wilson wrote: > In commit 25ff1195f8a0b3724541ae7bbe331b4296de9c06 > Author: Chris Wilson <chris at chris-wilson.co.uk> > Date: Thu Apr 4 21:31:03 2013 +0100 > > drm/i915: Workaround incoherence between fences and LLC across multiple CPUs > > we introduced an empirical workaround for memory corruption when using > fences from multiple CPUs. At the time, we did not have any results for > Valleyview, so the presumption was that it was limited to recent > generations using LLC. Now we have evidence that Valleyview also suffers > incoherence and requires a similar but different workaround. For > Valleyview, the wbinvd instruction is insufficient and we require the > serialising register write per-CPU. Conversely, that serialising > register write is not enough for SNB/IVB/HSW. To compromise and keep the > code relatively clean, employ both serialisation techniques in the same > workaround. > > Reported-by: Jon Bloomfield <jon.bloomfield at intel.com> > Tested-by: Jon Bloomfield <jon.bloomfield at intel.com> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62191 > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Queued for -next (since vlv isn't yet declared stable in 3.10), thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
