On Mon, 19 Jul 2021, Khaled Almahallawy <khaled.almahallawy@xxxxxxxxx> wrote:
> Bits 20:19 are used to set CP2520 Patterns 1/2/3 (refer to Specs:50484).
> TPS4 is CP2520 Pattern 3 (refer to DP2.0 spaces Table 3-11, DPCD 00248h
> LINK_QUAL_PATTERN_SELECT, and DP PHY 1.4 CTS - Appendix A - Compliance
> EYE Pattern(CP2520; Normative))
>
> For TPS4, setting bits 20:19 to value != 00b, leads to a non-TPS4 pattern.
> This is confirmed using DP Scope running DP1.4 PHY CTS.
>
> To avoid any accidental wrong setting of bits 20:19, set it correctly for
> TPS4 LT pattern selection. This programming sequence is the same used by EV.
Do we need this?
BR,
Jani.
>
> Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> CC: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 26a3aa73fcc4..54b4b28fdc74 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3412,6 +3412,8 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
> break;
> case DP_TRAINING_PATTERN_4:
> temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
> + temp &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
> + temp |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a;
> break;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 943fe485c662..a65998df9994 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10176,6 +10176,10 @@ enum skl_power_gate {
> #define DP_TP_CTL_MODE_SST (0 << 27)
> #define DP_TP_CTL_MODE_MST (1 << 27)
> #define DP_TP_CTL_FORCE_ACT (1 << 25)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
> #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
> #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
> #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
--
Jani Nikula, Intel Open Source Graphics Center
