On Tue, May 21, 2013 at 02:52:24PM +0200, Daniel Vetter wrote: > On Tue, May 21, 2013 at 2:35 PM, Ville Syrj?l? > <ville.syrjala at linux.intel.com> wrote: > > On Tue, May 21, 2013 at 03:28:32PM +0300, ville.syrjala at linux.intel.com wrote: > >> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > >> > >> The docs say that the trickle feed disable bit is present (for primary > >> planes only, not video sprites) on CTG, and that it must be set > >> for ELK. Just set it for all g4x chipsets. > >> > >> v2: Do it in init_clock_gating too > > > > Actually I just noticed that we don't set up this stuff in > > ironlake_init_clock_gating() either. Any opinions whether I should just > > kill the per-plane trickle feed stuff from *_init_clock_gating(), or > > should I add it to ironlake_init_clock_gating() as well? > > This is a bit a crazy topic since conceptually it ties into the > wm/pipe-config stuff. And fastboot will make this stuff rather > interesting ... I expect that we'll eventually end up with a > post_modeset_fixup stage to patch up all these little bits&pieces - > fastboot would only call that one if possible. I'd expect we do at least a set_base w/ fastboot, which would take care of the per-plane trickle feed bit. But I don't care much either way at this point. I'll post a quick patch for ironlake_init_clock_gating() just to keep these things at least somewhat consistent... -- Ville Syrj?l? Intel OTC
