On Wed, 06 Oct 2021, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Use <4 instead of <=3 as the terminating condition for the
> loops over the 4 lanes.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d85d731e37fb..b0bd50383d57 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1067,7 +1067,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>
> /* Program PORT_TX_DW4 */
> /* We cannot write to GRP. It would overwrite individual loadgen. */
> - for (ln = 0; ln <= 3; ln++) {
> + for (ln = 0; ln < 4; ln++) {
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> CURSOR_COEFF_MASK);
> @@ -1114,7 +1114,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
> * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
> * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
> */
> - for (ln = 0; ln <= 3; ln++) {
> + for (ln = 0; ln < 4; ln++) {
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
> val &= ~LOADGEN_SELECT;
--
Jani Nikula, Intel Open Source Graphics Center
