On Mon, Oct 04, 2021 at 10:50:00AM -0700, Matt Roper wrote: > On Sat, Oct 02, 2021 at 01:01:31AM +0300, Ville Syrjälä wrote: > > On Fri, Oct 01, 2021 at 02:08:15PM -0700, Matt Roper wrote: > > > On Thu, Sep 30, 2021 at 10:09:42PM +0300, Ville Syrjala wrote: > > > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > > > > > Looks like skl/bxt/derivatives also need the plane stride > > > > stretch w/a when using async flips and VT-d is enabled, or > > > > else we get corruption on screen. To my surprise this was > > > > even documented in bspec, but only as a note on the > > > > CHICHKEN_PIPESL register description rather than on the > > > > w/a list. > > > > > > > > So very much the same thing as on HSW/BDW, except the bits > > > > moved yet again. > > > > > > Bspec 7522 doesn't say anything about this requirement being tied to > > > VT-d on these platforms. Should we drop the intel_vtd_active() > > > condition to be safe? > > > > I think it's just an oversight in bspec. I read through the hsd and > > IIRC it did specify that it's VT-d only. Also real life confirms > > it. No problems whatsoever when VT-d is disabled. > > I notice there are additional bits that we should set to apply this > workaround to planes 2, 3, and 4, but since i915 still artificially > limits async flips to just the primary plane, only programming bits 1:0 > should be fine for now; we'll just need to remember to extend this > workaround if we do start allowing async flips on other planes in the > future. Aye. gen8_de_pipe_flip_done_mask() is the other place where we still hardcode this for plane 1 only. I think the rest of the code I did end up making more or less plane agnostic already. I was considering at least parametrizing the register defines but then I got a nagging feeling that I once ran into some issues while trying to stick non-constant numbers into REG_BIT & co. So I decided to hardcode plane 1 for the moment. > > Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx> Thanks. Pushed. -- Ville Syrjälä Intel
