From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> A little bit more generic DP link training improvements before we finally get to the actual per-lane drive settings PHY programming stuff. v2: CI is confused about sha1s for some reason Ville Syrjälä (5): drm/i915: Tweak the DP "max vswing reached?" condition drm/i915: Show LTTPR in the TPS debug print drm/i915: Print the DP vswing adjustment request drm/i915: Pimp link training debug prints drm/i915: Call intel_dp_dump_link_status() for CR failures drivers/gpu/drm/i915/display/g4x_dp.c | 2 +- .../drm/i915/display/intel_dp_link_training.c | 217 +++++++++++++----- .../drm/i915/display/intel_dp_link_training.h | 1 + 3 files changed, 157 insertions(+), 63 deletions(-) -- 2.32.0
