On Tue, 2021-09-21 at 03:23 +0300, Imre Deak wrote: > The PHY ownership release->AUX PW disable steps during a modeset > disable->PHY disconnect sequence can hang the system if the PHY > disconnect happens after disabling the PHY's PLL. The spec doesn't > require a specific order for these two steps, so this issue is still > being root caused by HW/FW teams. Until that is found, let's make > sure the disconnect happens before the PLL is disabled, and do this on > all platforms for consistency. > > Cc: José Roberto de Souza <jose.souza@xxxxxxxxx> > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_tc.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c > index 99b66c2852e53..dc52b76bd57e2 100644 > --- a/drivers/gpu/drm/i915/display/intel_tc.c > +++ b/drivers/gpu/drm/i915/display/intel_tc.c > @@ -813,6 +813,12 @@ void intel_tc_port_put_link(struct intel_digital_port *dig_port) > intel_tc_port_lock(dig_port); > --dig_port->tc_link_refcount; > intel_tc_port_unlock(dig_port); > + > + /* > + * Disconnecting the PHY after the PHY's PLL gets disabled may > + * hang the system on ADL-P, so disconnect the PHY here synchronously. > + */ Please at to the comment that this is temporary while HW/FW teaams root cause it. With that: Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > + intel_tc_port_flush_work(dig_port); > } > > static bool
