> -----Original Message-----
> From: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
> Sent: Friday, September 24, 2021 7:44 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Shankar, Uma <uma.shankar@xxxxxxxxx>
> Subject: [PATCH] drm/i915/fbc: Allow FBC with Yf tiling
>
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> FBC+Yf tiling seems to work just fine, and unlike with linear
> the hardware does appear to correctly calculate the CFB stride with using the
> override stride on both cfl and glk. So no need for any additional tweaks.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> Cc: Uma Shankar <uma.shankar@xxxxxxxxx> #v2
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 46f62fdf9eee..687431faf02f 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -746,6 +746,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> switch (modifier) {
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_Yf_TILED:
> return DISPLAY_VER(dev_priv) >= 9;
> case I915_FORMAT_MOD_X_TILED:
> return true;
> --
> 2.32.0
