On Thu, May 09, 2013 at 02:20:50PM -0300, Rodrigo Vivi wrote:
> Display register 46500h bit 23 must be set to 1b for the entire time that
> Frame Buffer Compression is enabled.
>
> v2: Ville suggested to enable it back when disabling fbc to avoid wasting
> power.
>
> v3: RMW to preserve other bits (by Ville)
> v4: Fix from Ville: sed &/| at RMW
> v5: Too far on sed.
>
> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com>
> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
I've slurped in the entire series into dinq (which a whitespace fix added
for this patch here), thanks for the patches and review.
I'll drop my reservations here about enabling fbc by default on haswell,
expect a "told you so" if it blows up ;-)
Cheers, Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a17480e..40a59e5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -986,6 +986,9 @@
> _HSW_PIPE_SLICE_CHICKEN_1_A, + \
> _HSW_PIPE_SLICE_CHICKEN_1_B)
>
> +#define HSW_CLKGATE_DISABLE_PART_1 0x46500
> +#define HSW_DPFC_GATING_DISABLE (1<<23)
> +
> /*
> * GPIO regs
> */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3f4bf58..aedf5da 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -248,6 +248,12 @@ static void ironlake_disable_fbc(struct drm_device *dev)
> I915_READ(ILK_DSPCLK_GATE_D) &
> ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
>
> + if(IS_HASWELL(dev))
> + /* WaFbcDisableDpfcClockGating */
> + I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
> + I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
> + ~HSW_DPFC_GATING_DISABLE);
> +
> DRM_DEBUG_KMS("disabled FBC\n");
> }
> }
> @@ -285,6 +291,10 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
> /* WaFbcAsynchFlipDisableFbcQueue */
> I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
> HSW_BYPASS_FBC_QUEUE);
> + /* WaFbcDisableDpfcClockGating */
> + I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
> + I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
> + HSW_DPFC_GATING_DISABLE);
> }
>
> I915_WRITE(SNB_DPFC_CTL_SA,
> --
> 1.7.11.7
>
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> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
