Bay Trail is the marketing name for the new Silvermont based SOCs we've
been calling Valleyview. All recent Intel disclosed documents use the
term "Bay Trail." AFAICT, only leaked docs (and our code) use the term
Valleyview. I've also verified with internal sources that references to,
"Valleyview" should be dropped.
Why?
We've always strived to make the already confusing generation
information as clear as possible in our driver. With the introduction
of the below, we made two names referring to the exact same silicon.
commit 93c34e70ebf464a9ee142d93b681c5df094ec654
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Apr 22 00:53:50 2013 -0700
drm/i915: Fix page table entries for Bay Trail.
While it's tempting to simply do the renames in Ken's patch, it's simply
not correct. As an added bonus, Mesa also uses the byt/baytrail names.
Yes. I know this is painful. Doing it now is the least painful way to do
this right (short of going back in time.)
disclaimer: only compile tested.
disclaimer2: I didn't fix pre-existing checkpatch issues.
CC: Kenneth Graunke <kenneth at whitecape.org>
CC: Jesse Barnes <jbarnes at virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
drivers/gpu/drm/i915/i915_debugfs.c | 50 +++----
drivers/gpu/drm/i915/i915_dma.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 26 ++--
drivers/gpu/drm/i915/i915_drv.h | 28 ++--
drivers/gpu/drm/i915/i915_gem.c | 10 +-
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +-
drivers/gpu/drm/i915/i915_gem_tiling.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 96 ++++++------
drivers/gpu/drm/i915/i915_reg.h | 154 +++++++++----------
drivers/gpu/drm/i915/i915_sysfs.c | 38 ++---
drivers/gpu/drm/i915/intel_crt.c | 14 +-
drivers/gpu/drm/i915/intel_display.c | 96 ++++++------
drivers/gpu/drm/i915/intel_dp.c | 90 +++++------
drivers/gpu/drm/i915/intel_drv.h | 6 +-
drivers/gpu/drm/i915/intel_hdmi.c | 42 +++---
drivers/gpu/drm/i915/intel_i2c.c | 4 +-
drivers/gpu/drm/i915/intel_pm.c | 232 ++++++++++++++---------------
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 24 +--
21 files changed, 462 insertions(+), 462 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a55630a..59ff8a8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -429,22 +429,22 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
if (ret)
return ret;
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_BAYTRAIL(dev)) {
seq_printf(m, "Display IER:\t%08x\n",
- I915_READ(VLV_IER));
+ I915_READ(BYT_IER));
seq_printf(m, "Display IIR:\t%08x\n",
- I915_READ(VLV_IIR));
+ I915_READ(BYT_IIR));
seq_printf(m, "Display IIR_RW:\t%08x\n",
- I915_READ(VLV_IIR_RW));
+ I915_READ(BYT_IIR_RW));
seq_printf(m, "Display IMR:\t%08x\n",
- I915_READ(VLV_IMR));
+ I915_READ(BYT_IMR));
for_each_pipe(pipe)
seq_printf(m, "Pipe %c stat:\t%08x\n",
pipe_name(pipe),
I915_READ(PIPESTAT(pipe)));
seq_printf(m, "Master IER:\t%08x\n",
- I915_READ(VLV_MASTER_IER));
+ I915_READ(BYT_MASTER_IER));
seq_printf(m, "Render IER:\t%08x\n",
I915_READ(GTIER));
@@ -463,7 +463,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
seq_printf(m, "Port hotplug:\t%08x\n",
I915_READ(PORT_HOTPLUG_EN));
seq_printf(m, "DPFLIPSTAT:\t%08x\n",
- I915_READ(VLV_DPFLIPSTAT));
+ I915_READ(BYT_DPFLIPSTAT));
seq_printf(m, "DPINVGTT:\t%08x\n",
I915_READ(DPINVGTT));
@@ -941,7 +941,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
MEMSTAT_VID_SHIFT);
seq_printf(m, "Current P-state: %d\n",
(rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
- } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
+ } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_BAYTRAIL(dev)) {
u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
@@ -1009,25 +1009,25 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
seq_printf(m, "Max overclocked frequency: %dMHz\n",
dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_BAYTRAIL(dev)) {
u32 freq_sts, val;
mutex_lock(&dev_priv->rps.hw_lock);
- valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS,
+ baytrail_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS,
&freq_sts);
seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
- valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val);
+ baytrail_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val);
seq_printf(m, "max GPU freq: %d MHz\n",
- vlv_gpu_freq(dev_priv->mem_freq, val));
+ byt_gpu_freq(dev_priv->mem_freq, val));
- valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
+ baytrail_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
seq_printf(m, "min GPU freq: %d MHz\n",
- vlv_gpu_freq(dev_priv->mem_freq, val));
+ byt_gpu_freq(dev_priv->mem_freq, val));
seq_printf(m, "current GPU freq: %d MHz\n",
- vlv_gpu_freq(dev_priv->mem_freq,
+ byt_gpu_freq(dev_priv->mem_freq,
(freq_sts >> 8) & 0xff));
mutex_unlock(&dev_priv->rps.hw_lock);
} else {
@@ -1651,7 +1651,7 @@ static int i915_dpio_info(struct seq_file *m, void *data)
int ret;
- if (!IS_VALLEYVIEW(dev)) {
+ if (!IS_BAYTRAIL(dev)) {
seq_printf(m, "unsupported\n");
return 0;
}
@@ -1833,8 +1833,8 @@ i915_max_freq_get(void *data, u64 *val)
if (ret)
return ret;
- if (IS_VALLEYVIEW(dev))
- *val = vlv_gpu_freq(dev_priv->mem_freq,
+ if (IS_BAYTRAIL(dev))
+ *val = byt_gpu_freq(dev_priv->mem_freq,
dev_priv->rps.max_delay);
else
*val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
@@ -1862,8 +1862,8 @@ i915_max_freq_set(void *data, u64 val)
/*
* Turbo will still be enabled, but won't go above the set value.
*/
- if (IS_VALLEYVIEW(dev)) {
- val = vlv_freq_opcode(dev_priv->mem_freq, val);
+ if (IS_BAYTRAIL(dev)) {
+ val = byt_freq_opcode(dev_priv->mem_freq, val);
dev_priv->rps.max_delay = val;
gen6_set_rps(dev, val);
} else {
@@ -1895,8 +1895,8 @@ i915_min_freq_get(void *data, u64 *val)
if (ret)
return ret;
- if (IS_VALLEYVIEW(dev))
- *val = vlv_gpu_freq(dev_priv->mem_freq,
+ if (IS_BAYTRAIL(dev))
+ *val = byt_gpu_freq(dev_priv->mem_freq,
dev_priv->rps.min_delay);
else
*val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
@@ -1924,10 +1924,10 @@ i915_min_freq_set(void *data, u64 val)
/*
* Turbo will still be enabled, but won't go below the set value.
*/
- if (IS_VALLEYVIEW(dev)) {
- val = vlv_freq_opcode(dev_priv->mem_freq, val);
+ if (IS_BAYTRAIL(dev)) {
+ val = byt_freq_opcode(dev_priv->mem_freq, val);
dev_priv->rps.min_delay = val;
- valleyview_set_rps(dev, val);
+ baytrail_set_rps(dev, val);
} else {
do_div(val, GT_FREQUENCY_MULTIPLIER);
dev_priv->rps.min_delay = val;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a1648eb..67ef9f6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1640,7 +1640,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
mutex_init(&dev_priv->modeset_restore_lock);
dev_priv->num_plane = 1;
- if (IS_VALLEYVIEW(dev))
+ if (IS_BAYTRAIL(dev))
dev_priv->num_plane = 2;
if (INTEL_INFO(dev)->num_pipes) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 40b5787..a6e3c1c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -288,20 +288,20 @@ static const struct intel_device_info intel_ivybridge_q_info = {
.num_pipes = 0, /* legal, last one wins */
};
-static const struct intel_device_info intel_valleyview_m_info = {
+static const struct intel_device_info intel_baytrail_m_info = {
GEN7_FEATURES,
.is_mobile = 1,
.num_pipes = 2,
- .is_valleyview = 1,
- .display_mmio_offset = VLV_DISPLAY_BASE,
+ .is_baytrail = 1,
+ .display_mmio_offset = BYT_DISPLAY_BASE,
.has_llc = 0, /* legal, last one wins */
};
-static const struct intel_device_info intel_valleyview_d_info = {
+static const struct intel_device_info intel_baytrail_d_info = {
GEN7_FEATURES,
.num_pipes = 2,
- .is_valleyview = 1,
- .display_mmio_offset = VLV_DISPLAY_BASE,
+ .is_baytrail = 1,
+ .display_mmio_offset = BYT_DISPLAY_BASE,
.has_llc = 0, /* legal, last one wins */
};
@@ -402,12 +402,12 @@ static const struct pci_device_id pciidlist[] = { /* aka */
INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
- INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
- INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
- INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
- INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
- INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
- INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
+ INTEL_VGA_DEVICE(0x0f30, &intel_baytrail_m_info),
+ INTEL_VGA_DEVICE(0x0f31, &intel_baytrail_m_info),
+ INTEL_VGA_DEVICE(0x0f32, &intel_baytrail_m_info),
+ INTEL_VGA_DEVICE(0x0f33, &intel_baytrail_m_info),
+ INTEL_VGA_DEVICE(0x0157, &intel_baytrail_m_info),
+ INTEL_VGA_DEVICE(0x0155, &intel_baytrail_d_info),
{0, 0, 0}
};
@@ -964,7 +964,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
struct intel_device_info *intel_info =
(struct intel_device_info *) ent->driver_data;
- if (intel_info->is_valleyview)
+ if (intel_info->is_baytrail)
if(!i915_preliminary_hw_support) {
DRM_ERROR("Preliminary hardware support disabled\n");
return -ENODEV;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c81100c..d692e11 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -363,7 +363,7 @@ struct drm_i915_gt_funcs {
func(is_broadwater) sep \
func(is_crestline) sep \
func(is_ivybridge) sep \
- func(is_valleyview) sep \
+ func(is_baytrail) sep \
func(is_haswell) sep \
func(has_force_wake) sep \
func(has_fbc) sep \
@@ -672,7 +672,7 @@ struct i915_suspend_saved_registers {
struct intel_gen6_power_mgmt {
struct work_struct work;
- struct delayed_work vlv_work;
+ struct delayed_work byt_work;
u32 pm_iir;
/* lock - irqsave spinlock that protectects the work_struct and
* pm_iir. */
@@ -1337,7 +1337,7 @@ struct drm_i915_file_private {
#define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
(dev)->pci_device == 0x0106 || \
(dev)->pci_device == 0x010A)
-#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
+#define IS_BAYTRAIL(dev) (INTEL_INFO(dev)->is_baytrail)
#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
#define IS_ULT(dev) (IS_HASWELL(dev) && \
@@ -1362,7 +1362,7 @@ struct drm_i915_file_private {
#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
-#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
+#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_BAYTRAIL(dev))
#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
@@ -1877,9 +1877,9 @@ extern void intel_disable_fbc(struct drm_device *dev);
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
extern void intel_init_pch_refclk(struct drm_device *dev);
extern void gen6_set_rps(struct drm_device *dev, u8 val);
-extern void valleyview_set_rps(struct drm_device *dev, u8 val);
-extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
-extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
+extern void baytrail_set_rps(struct drm_device *dev, u8 val);
+extern int baytrail_rps_max_freq(struct drm_i915_private *dev_priv);
+extern int baytrail_rps_min_freq(struct drm_i915_private *dev_priv);
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
extern int intel_enable_rc6(const struct drm_device *dev);
@@ -1909,12 +1909,12 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
-int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
-int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
-int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
+int baytrail_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
+int baytrail_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
+int baytrail_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
-int vlv_gpu_freq(int ddr_freq, int val);
-int vlv_freq_opcode(int ddr_freq, int val);
+int byt_gpu_freq(int ddr_freq, int val);
+int byt_freq_opcode(int ddr_freq, int val);
#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
@@ -1962,8 +1962,8 @@ static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
{
if (HAS_PCH_SPLIT(dev))
return CPU_VGACNTRL;
- else if (IS_VALLEYVIEW(dev))
- return VLV_VGACNTRL;
+ else if (IS_BAYTRAIL(dev))
+ return BYT_VGACNTRL;
else
return VGACNTRL;
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a1a282c..545f344 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4057,10 +4057,10 @@ int i915_gem_init(struct drm_device *dev)
mutex_lock(&dev->struct_mutex);
- if (IS_VALLEYVIEW(dev)) {
- /* VLVA0 (potential hack), BIOS isn't actually waking us */
- I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
- if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
+ if (IS_BAYTRAIL(dev)) {
+ /* BYTA0 (potential hack), BIOS isn't actually waking us */
+ I915_WRITE(BYT_GTLC_WAKE_CTRL, 1);
+ if (wait_for((I915_READ(BYT_GTLC_PW_STATUS) & 1) == 1, 10))
DRM_DEBUG_DRIVER("allow wake ack timed out\n");
}
@@ -4200,7 +4200,7 @@ i915_gem_load(struct drm_device *dev)
if (!drm_core_check_feature(dev, DRIVER_MODESET))
dev_priv->fence_reg_start = 3;
- if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
+ if (INTEL_INFO(dev)->gen >= 7 && !IS_BAYTRAIL(dev))
dev_priv->num_fence_regs = 32;
else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
dev_priv->num_fence_regs = 16;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 64cb190..d8701b8 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -333,7 +333,7 @@ mi_set_context(struct intel_ring_buffer *ring,
if (ret)
return ret;
- /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
+ /* WaProgramMiArbOnOffAroundMiSetContext:ivb,byt,hsw */
if (IS_GEN7(ring->dev))
intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
else
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 117ce38..f22fc3c 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1012,7 +1012,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
}
batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
- /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
+ /* snb/ivb/byt conflate the "batch in ppgtt" bit with the "non-secure
* batch" bit. Hence we need to pin secure batches into the global gtt.
* hsw should have this fixed, but let's be paranoid and do it
* unconditionally for now. */
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ddad13f..a20d7ec 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -273,7 +273,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
if (IS_HASWELL(dev)) {
ppgtt->pte_encode = hsw_pte_encode;
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_BAYTRAIL(dev)) {
ppgtt->pte_encode = byt_pte_encode;
} else {
ppgtt->pte_encode = gen6_pte_encode;
@@ -856,7 +856,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
dev_priv->gtt.gtt_remove = gen6_gmch_remove;
if (IS_HASWELL(dev)) {
dev_priv->gtt.pte_encode = hsw_pte_encode;
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_BAYTRAIL(dev)) {
dev_priv->gtt.pte_encode = byt_pte_encode;
} else {
dev_priv->gtt.pte_encode = gen6_pte_encode;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 537545b..560aea1 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -91,7 +91,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_BAYTRAIL(dev)) {
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
} else if (INTEL_INFO(dev)->gen >= 6) {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 879c4cc..36c4e98 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -79,7 +79,7 @@ static const u32 hpd_status_i965[] = {
[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};
-static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
+static const u32 hpd_status_i915[] = { /* i915 and baytrail are the same */
[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
@@ -716,20 +716,20 @@ static void gen6_pm_rps_work(struct work_struct *work)
*/
if (!(new_delay > dev_priv->rps.max_delay ||
new_delay < dev_priv->rps.min_delay)) {
- if (IS_VALLEYVIEW(dev_priv->dev))
- valleyview_set_rps(dev_priv->dev, new_delay);
+ if (IS_BAYTRAIL(dev_priv->dev))
+ baytrail_set_rps(dev_priv->dev, new_delay);
else
gen6_set_rps(dev_priv->dev, new_delay);
}
- if (IS_VALLEYVIEW(dev_priv->dev)) {
+ if (IS_BAYTRAIL(dev_priv->dev)) {
/*
- * On VLV, when we enter RC6 we may not be at the minimum
+ * On BYT, when we enter RC6 we may not be at the minimum
* voltage level, so arm a timer to check. It should only
* fire when there's activity or once after we've entered
* RC6, and then won't be re-armed until the next RPS interrupt.
*/
- mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
+ mod_delayed_work(dev_priv->wq, &dev_priv->rps.byt_work,
msecs_to_jiffies(100));
}
@@ -919,7 +919,7 @@ static void dp_aux_irq_handler(struct drm_device *dev)
wake_up_all(&dev_priv->gmbus_wait_queue);
}
-static irqreturn_t valleyview_irq_handler(int irq, void *arg)
+static irqreturn_t baytrail_irq_handler(int irq, void *arg)
{
struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -932,7 +932,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
atomic_inc(&dev_priv->irq_received);
while (true) {
- iir = I915_READ(VLV_IIR);
+ iir = I915_READ(BYT_IIR);
gt_iir = I915_READ(GTIIR);
pm_iir = I915_READ(GEN6_PMIIR);
@@ -964,7 +964,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
drm_handle_vblank(dev, pipe);
- if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
+ if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_BYT) {
intel_prepare_page_flip(dev, pipe);
intel_finish_page_flip(dev, pipe);
}
@@ -995,7 +995,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
I915_WRITE(GTIIR, gt_iir);
I915_WRITE(GEN6_PMIIR, pm_iir);
- I915_WRITE(VLV_IIR, iir);
+ I915_WRITE(BYT_IIR, iir);
}
out:
@@ -1852,8 +1852,8 @@ static void i915_capture_error_state(struct drm_device *dev)
if (HAS_PCH_SPLIT(dev))
error->ier = I915_READ(DEIER) | I915_READ(GTIER);
- else if (IS_VALLEYVIEW(dev))
- error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
+ else if (IS_BAYTRAIL(dev))
+ error->ier = I915_READ(GTIER) | I915_READ(BYT_IER);
else if (IS_GEN2(dev))
error->ier = I915_READ16(IER);
else
@@ -1862,8 +1862,8 @@ static void i915_capture_error_state(struct drm_device *dev)
if (INTEL_INFO(dev)->gen >= 6)
error->derrmr = I915_READ(DERRMR);
- if (IS_VALLEYVIEW(dev))
- error->forcewake = I915_READ(FORCEWAKE_VLV);
+ if (IS_BAYTRAIL(dev))
+ error->forcewake = I915_READ(FORCEWAKE_BYT);
else if (INTEL_INFO(dev)->gen >= 7)
error->forcewake = I915_READ(FORCEWAKE_MT);
else if (INTEL_INFO(dev)->gen == 6)
@@ -2186,7 +2186,7 @@ static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
return 0;
}
-static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
+static int baytrail_enable_vblank(struct drm_device *dev, int pipe)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
unsigned long irqflags;
@@ -2196,12 +2196,12 @@ static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
return -EINVAL;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- imr = I915_READ(VLV_IMR);
+ imr = I915_READ(BYT_IMR);
if (pipe == 0)
imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
else
imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
- I915_WRITE(VLV_IMR, imr);
+ I915_WRITE(BYT_IMR, imr);
i915_enable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_ENABLE);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -2249,7 +2249,7 @@ static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
-static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
+static void baytrail_disable_vblank(struct drm_device *dev, int pipe)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
unsigned long irqflags;
@@ -2258,12 +2258,12 @@ static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
i915_disable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_ENABLE);
- imr = I915_READ(VLV_IMR);
+ imr = I915_READ(BYT_IMR);
if (pipe == 0)
imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
else
imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
- I915_WRITE(VLV_IMR, imr);
+ I915_WRITE(BYT_IMR, imr);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
@@ -2470,15 +2470,15 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
POSTING_READ(SDEIER);
}
-static void valleyview_irq_preinstall(struct drm_device *dev)
+static void baytrail_irq_preinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
int pipe;
atomic_set(&dev_priv->irq_received, 0);
- /* VLV magic */
- I915_WRITE(VLV_IMR, 0);
+ /* BYT magic */
+ I915_WRITE(BYT_IMR, 0);
I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
@@ -2496,10 +2496,10 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
for_each_pipe(pipe)
I915_WRITE(PIPESTAT(pipe), 0xffff);
- I915_WRITE(VLV_IIR, 0xffffffff);
- I915_WRITE(VLV_IMR, 0xffffffff);
- I915_WRITE(VLV_IER, 0x0);
- POSTING_READ(VLV_IER);
+ I915_WRITE(BYT_IIR, 0xffffffff);
+ I915_WRITE(BYT_IMR, 0xffffffff);
+ I915_WRITE(BYT_IER, 0x0);
+ POSTING_READ(BYT_IER);
}
static void ibx_hpd_irq_setup(struct drm_device *dev)
@@ -2648,11 +2648,11 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
return 0;
}
-static int valleyview_irq_postinstall(struct drm_device *dev)
+static int baytrail_irq_postinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
u32 enable_mask;
- u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
+ u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_BYT;
u32 render_irqs;
enable_mask = I915_DISPLAY_PORT_INTERRUPT;
@@ -2672,19 +2672,19 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
I915_WRITE(PORT_HOTPLUG_EN, 0);
POSTING_READ(PORT_HOTPLUG_EN);
- I915_WRITE(VLV_IMR, dev_priv->irq_mask);
- I915_WRITE(VLV_IER, enable_mask);
- I915_WRITE(VLV_IIR, 0xffffffff);
+ I915_WRITE(BYT_IMR, dev_priv->irq_mask);
+ I915_WRITE(BYT_IER, enable_mask);
+ I915_WRITE(BYT_IIR, 0xffffffff);
I915_WRITE(PIPESTAT(0), 0xffff);
I915_WRITE(PIPESTAT(1), 0xffff);
- POSTING_READ(VLV_IER);
+ POSTING_READ(BYT_IER);
i915_enable_pipestat(dev_priv, 0, pipestat_enable);
i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
i915_enable_pipestat(dev_priv, 1, pipestat_enable);
- I915_WRITE(VLV_IIR, 0xffffffff);
- I915_WRITE(VLV_IIR, 0xffffffff);
+ I915_WRITE(BYT_IIR, 0xffffffff);
+ I915_WRITE(BYT_IIR, 0xffffffff);
I915_WRITE(GTIIR, I915_READ(GTIIR));
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
@@ -2700,12 +2700,12 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif
- I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
+ I915_WRITE(BYT_MASTER_IER, MASTER_INTERRUPT_ENABLE);
return 0;
}
-static void valleyview_irq_uninstall(struct drm_device *dev)
+static void baytrail_irq_uninstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
int pipe;
@@ -2723,10 +2723,10 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
for_each_pipe(pipe)
I915_WRITE(PIPESTAT(pipe), 0xffff);
- I915_WRITE(VLV_IIR, 0xffffffff);
- I915_WRITE(VLV_IMR, 0xffffffff);
- I915_WRITE(VLV_IER, 0x0);
- POSTING_READ(VLV_IER);
+ I915_WRITE(BYT_IIR, 0xffffffff);
+ I915_WRITE(BYT_IMR, 0xffffffff);
+ I915_WRITE(BYT_IER, 0x0);
+ POSTING_READ(BYT_IER);
}
static void ironlake_irq_uninstall(struct drm_device *dev)
@@ -3449,13 +3449,13 @@ void intel_irq_init(struct drm_device *dev)
dev->driver->get_vblank_timestamp = NULL;
dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
- if (IS_VALLEYVIEW(dev)) {
- dev->driver->irq_handler = valleyview_irq_handler;
- dev->driver->irq_preinstall = valleyview_irq_preinstall;
- dev->driver->irq_postinstall = valleyview_irq_postinstall;
- dev->driver->irq_uninstall = valleyview_irq_uninstall;
- dev->driver->enable_vblank = valleyview_enable_vblank;
- dev->driver->disable_vblank = valleyview_disable_vblank;
+ if (IS_BAYTRAIL(dev)) {
+ dev->driver->irq_handler = baytrail_irq_handler;
+ dev->driver->irq_preinstall = baytrail_irq_preinstall;
+ dev->driver->irq_postinstall = baytrail_irq_postinstall;
+ dev->driver->irq_uninstall = baytrail_irq_uninstall;
+ dev->driver->enable_vblank = baytrail_enable_vblank;
+ dev->driver->disable_vblank = baytrail_disable_vblank;
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
/* Share pre & uninstall handlers with ILK/SNB */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4e5315a..2a4d417 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -149,7 +149,7 @@
/*
* SR01 is the only VGA register touched on non-UMS setups.
- * VLV doesn't do UMS, so the sequencer index/data registers
+ * BYT doesn't do UMS, so the sequencer index/data registers
* are the only VGA registers which need to include
* display_mmio_offset.
*/
@@ -254,7 +254,7 @@
#define MI_FLUSH_DW_USE_PPGTT (0<<2)
#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
#define MI_BATCH_NON_SECURE (1)
-/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
+/* for snb/ivb/byt this also means "batch in ppgtt" when ppgtt is enabled. */
#define MI_BATCH_NON_SECURE_I965 (1<<8)
#define MI_BATCH_PPGTT_HSW (1<<8)
#define MI_BATCH_NON_SECURE_HSW (1<<13)
@@ -350,20 +350,20 @@
* 0x8048/68: low pass filter coefficients
* 0x8100: fast clock controls
*
- * DPIO is VLV only.
+ * DPIO is BYT only.
*
* Note: digital port B is DDI0, digital pot C is DDI1
*/
-#define DPIO_PKT (VLV_DISPLAY_BASE + 0x2100)
+#define DPIO_PKT (BYT_DISPLAY_BASE + 0x2100)
#define DPIO_RID (0<<24)
#define DPIO_OP_WRITE (1<<16)
#define DPIO_OP_READ (0<<16)
#define DPIO_PORTID (0x12<<8)
#define DPIO_BYTE (0xf<<4)
#define DPIO_BUSY (1<<0) /* status only */
-#define DPIO_DATA (VLV_DISPLAY_BASE + 0x2104)
-#define DPIO_REG (VLV_DISPLAY_BASE + 0x2108)
-#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
+#define DPIO_DATA (BYT_DISPLAY_BASE + 0x2104)
+#define DPIO_REG (BYT_DISPLAY_BASE + 0x2108)
+#define DPIO_CTL (BYT_DISPLAY_BASE + 0x2110)
#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
#define DPIO_SFR_BYPASS (1<<1)
@@ -684,20 +684,20 @@
#define GFX_PSMI_GRANULARITY (1<<10)
#define GFX_PPGTT_ENABLE (1<<9)
-#define VLV_DISPLAY_BASE 0x180000
+#define BYT_DISPLAY_BASE 0x180000
#define SCPD0 0x0209c /* 915+ only */
#define IER 0x020a0
#define IIR 0x020a4
#define IMR 0x020a8
#define ISR 0x020ac
-#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
+#define BYT_GUNIT_CLOCK_GATE (BYT_DISPLAY_BASE + 0x2060)
#define GCFG_DIS (1<<8)
-#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
-#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
-#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
-#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
-#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
+#define BYT_IIR_RW (BYT_DISPLAY_BASE + 0x2084)
+#define BYT_IER (BYT_DISPLAY_BASE + 0x20a0)
+#define BYT_IIR (BYT_DISPLAY_BASE + 0x20a4)
+#define BYT_IMR (BYT_DISPLAY_BASE + 0x20a8)
+#define BYT_ISR (BYT_DISPLAY_BASE + 0x20ac)
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
@@ -1063,9 +1063,9 @@
#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
#define DPLL_VCO_ENABLE (1 << 31)
#define DPLL_DVO_HIGH_SPEED (1 << 30)
-#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
+#define DPLL_EXT_BUFFER_ENABLE_BYT (1 << 30)
#define DPLL_SYNCLOCK_ENABLE (1 << 29)
-#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
+#define DPLL_REFA_CLK_ENABLE_BYT (1 << 29)
#define DPLL_VGA_MODE_DIS (1 << 28)
#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
@@ -1077,9 +1077,9 @@
#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
-#define DPLL_LOCK_VLV (1<<15)
-#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
-#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
+#define DPLL_LOCK_BYT (1<<15)
+#define DPLL_INTEGRATED_CRI_CLK_BYT (1<<14)
+#define DPLL_INTEGRATED_CLOCK_BYT (1<<13)
#define DPLL_PORTC_READY_MASK (0xf << 4)
#define DPLL_PORTB_READY_MASK (0xf)
@@ -1301,7 +1301,7 @@
#define RAMCLK_GATE_D 0x6210 /* CRL only */
#define DEUC 0x6214 /* CRL only */
-#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
+#define FW_BLC_SELF_BYT (BYT_DISPLAY_BASE + 0x6500)
#define FW_CSPWRDWNEN (1<<15)
/*
@@ -1715,7 +1715,7 @@
/* VGA port control */
#define ADPA 0x61100
#define PCH_ADPA 0xe1100
-#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
+#define BYT_ADPA (BYT_DISPLAY_BASE + ADPA)
#define ADPA_DAC_ENABLE (1<<31)
#define ADPA_DAC_DISABLE 0
@@ -2852,30 +2852,30 @@
#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
#define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024)
#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
-#define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30)
+#define SPRITE1_FLIPDONE_INT_EN_BYT (1UL<<30)
#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
#define PIPE_CRC_DONE_ENABLE (1UL<<28)
#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
-#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
+#define PLANE_FLIP_DONE_INT_EN_BYT (1UL<<26)
#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
-#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
+#define SPRITE0_FLIP_DONE_INT_EN_BYT (1UL<<22)
#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
-#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
+#define PIPEA_HBLANK_INT_EN_BYT (1UL<<16)
#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
-#define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15)
-#define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<14)
+#define SPRITE1_FLIPDONE_INT_STATUS_BYT (1UL<<15)
+#define SPRITE0_FLIPDONE_INT_STATUS_BYT (1UL<<14)
#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
-#define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10)
+#define PLANE_FLIPDONE_INT_STATUS_BYT (1UL<<10)
#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
@@ -2895,7 +2895,7 @@
#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
-#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
+#define BYT_DPFLIPSTAT (BYT_DISPLAY_BASE + 0x70028)
#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
#define PIPEB_HLINE_INT_EN (1<<28)
#define PIPEB_VBLANK_INT_EN (1<<27)
@@ -2909,7 +2909,7 @@
#define SPRITEA_FLIPDONE_INT_EN (1<<17)
#define PLANEA_FLIPDONE_INT_EN (1<<16)
-#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
+#define DPINVGTT (BYT_DISPLAY_BASE + 0x7002c) /* BYT only */
#define CURSORB_INVALID_GTT_INT_EN (1<<23)
#define CURSORA_INVALID_GTT_INT_EN (1<<22)
#define SPRITED_INVALID_GTT_INT_EN (1<<21)
@@ -2963,13 +2963,13 @@
/* drain latency register values*/
#define DRAIN_LATENCY_PRECISION_32 32
#define DRAIN_LATENCY_PRECISION_16 16
-#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
+#define BYT_DDL1 (BYT_DISPLAY_BASE + 0x70050)
#define DDL_CURSORA_PRECISION_32 (1<<31)
#define DDL_CURSORA_PRECISION_16 (0<<31)
#define DDL_CURSORA_SHIFT 24
#define DDL_PLANEA_PRECISION_32 (1<<7)
#define DDL_PLANEA_PRECISION_16 (0<<7)
-#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
+#define BYT_DDL2 (BYT_DISPLAY_BASE + 0x70054)
#define DDL_CURSORB_PRECISION_32 (1<<31)
#define DDL_CURSORB_PRECISION_16 (0<<31)
#define DDL_CURSORB_SHIFT 24
@@ -2981,7 +2981,7 @@
#define I915_FIFO_LINE_SIZE 64
#define I830_FIFO_LINE_SIZE 32
-#define VALLEYVIEW_FIFO_SIZE 255
+#define BAYTRAIL_FIFO_SIZE 255
#define G4X_FIFO_SIZE 127
#define I965_FIFO_SIZE 512
#define I945_FIFO_SIZE 127
@@ -2989,7 +2989,7 @@
#define I855GM_FIFO_SIZE 127 /* In cachelines */
#define I830_FIFO_SIZE 95
-#define VALLEYVIEW_MAX_WM 0xff
+#define BAYTRAIL_MAX_WM 0xff
#define G4X_MAX_WM 0x3f
#define I915_MAX_WM 0x3f
@@ -3004,7 +3004,7 @@
#define PINEVIEW_CURSOR_DFT_WM 0
#define PINEVIEW_CURSOR_GUARD_WM 5
-#define VALLEYVIEW_CURSOR_MAX_WM 64
+#define BAYTRAIL_CURSOR_MAX_WM 64
#define I965_CURSOR_FIFO 64
#define I965_CURSOR_MAX_WM 32
#define I965_CURSOR_DFT_WM 8
@@ -3479,7 +3479,7 @@
# define VGA_2X_MODE (1 << 30)
# define VGA_PIPE_B_SELECT (1 << 29)
-#define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
+#define BYT_VGACNTRL (BYT_DISPLAY_BASE + 0x71400)
/* Ironlake */
@@ -3639,7 +3639,7 @@
#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
#define DE_PIPEA_VBLANK_IVB (1<<0)
-#define VLV_MASTER_IER 0x4400c /* Gunit master IER */
+#define BYT_MASTER_IER 0x4400c /* Gunit master IER */
#define MASTER_INTERRUPT_ENABLE (1<<31)
#define DEISR 0x44000
@@ -3966,20 +3966,20 @@
#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
-#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
-#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
-#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
+#define BYT_VIDEO_DIP_CTL_A (BYT_DISPLAY_BASE + 0x60200)
+#define BYT_VIDEO_DIP_DATA_A (BYT_DISPLAY_BASE + 0x60208)
+#define BYT_VIDEO_DIP_GDCP_PAYLOAD_A (BYT_DISPLAY_BASE + 0x60210)
-#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
-#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
-#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
+#define BYT_VIDEO_DIP_CTL_B (BYT_DISPLAY_BASE + 0x61170)
+#define BYT_VIDEO_DIP_DATA_B (BYT_DISPLAY_BASE + 0x61174)
+#define BYT_VIDEO_DIP_GDCP_PAYLOAD_B (BYT_DISPLAY_BASE + 0x61178)
-#define VLV_TVIDEO_DIP_CTL(pipe) \
- _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
-#define VLV_TVIDEO_DIP_DATA(pipe) \
- _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
-#define VLV_TVIDEO_DIP_GCP(pipe) \
- _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
+#define BYT_TVIDEO_DIP_CTL(pipe) \
+ _PIPE(pipe, BYT_VIDEO_DIP_CTL_A, BYT_VIDEO_DIP_CTL_B)
+#define BYT_TVIDEO_DIP_DATA(pipe) \
+ _PIPE(pipe, BYT_VIDEO_DIP_DATA_A, BYT_VIDEO_DIP_DATA_B)
+#define BYT_TVIDEO_DIP_GCP(pipe) \
+ _PIPE(pipe, BYT_VIDEO_DIP_GDCP_PAYLOAD_A, BYT_VIDEO_DIP_GDCP_PAYLOAD_B)
/* Haswell DIP controls */
#define HSW_VIDEO_DIP_CTL_A 0x60200
@@ -4234,26 +4234,26 @@
#define PCH_LVDS 0xe1180
#define LVDS_DETECTED (1 << 1)
-/* vlv has 2 sets of panel control regs. */
-#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
-#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
-#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
-#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
-#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
-
-#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
-#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
-#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
-#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
-#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
-
-#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
-#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
-#define VLV_PIPE_PP_ON_DELAYS(pipe) \
+/* byt has 2 sets of panel control regs. */
+#define PIPEA_PP_STATUS (BYT_DISPLAY_BASE + 0x61200)
+#define PIPEA_PP_CONTROL (BYT_DISPLAY_BASE + 0x61204)
+#define PIPEA_PP_ON_DELAYS (BYT_DISPLAY_BASE + 0x61208)
+#define PIPEA_PP_OFF_DELAYS (BYT_DISPLAY_BASE + 0x6120c)
+#define PIPEA_PP_DIVISOR (BYT_DISPLAY_BASE + 0x61210)
+
+#define PIPEB_PP_STATUS (BYT_DISPLAY_BASE + 0x61300)
+#define PIPEB_PP_CONTROL (BYT_DISPLAY_BASE + 0x61304)
+#define PIPEB_PP_ON_DELAYS (BYT_DISPLAY_BASE + 0x61308)
+#define PIPEB_PP_OFF_DELAYS (BYT_DISPLAY_BASE + 0x6130c)
+#define PIPEB_PP_DIVISOR (BYT_DISPLAY_BASE + 0x61310)
+
+#define BYT_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
+#define BYT_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
+#define BYT_PIPE_PP_ON_DELAYS(pipe) \
_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
-#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
+#define BYT_PIPE_PP_OFF_DELAYS(pipe) \
_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
-#define VLV_PIPE_PP_DIVISOR(pipe) \
+#define BYT_PIPE_PP_DIVISOR(pipe) \
_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
#define PCH_PP_STATUS 0xc7200
@@ -4383,14 +4383,14 @@
#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
#define FORCEWAKE 0xA18C
-#define FORCEWAKE_VLV 0x1300b0
-#define FORCEWAKE_ACK_VLV 0x1300b4
-#define FORCEWAKE_MEDIA_VLV 0x1300b8
-#define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
+#define FORCEWAKE_BYT 0x1300b0
+#define FORCEWAKE_ACK_BYT 0x1300b4
+#define FORCEWAKE_MEDIA_BYT 0x1300b8
+#define FORCEWAKE_ACK_MEDIA_BYT 0x1300bc
#define FORCEWAKE_ACK_HSW 0x130044
#define FORCEWAKE_ACK 0x130090
-#define VLV_GTLC_WAKE_CTRL 0x130090
-#define VLV_GTLC_PW_STATUS 0x130094
+#define BYT_GTLC_WAKE_CTRL 0x130090
+#define BYT_GTLC_PW_STATUS 0x130094
#define FORCEWAKE_MT 0xa188 /* multi-threaded */
#define FORCEWAKE_KERNEL 0x1
#define FORCEWAKE_USER 0x2
@@ -4518,7 +4518,7 @@
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
-#define VLV_IOSF_DOORBELL_REQ 0x182100
+#define BYT_IOSF_DOORBELL_REQ 0x182100
#define IOSF_DEVFN_SHIFT 24
#define IOSF_OPCODE_SHIFT 16
#define IOSF_PORT_SHIFT 8
@@ -4527,8 +4527,8 @@
#define IOSF_SB_BUSY (1<<0)
#define IOSF_PORT_PUNIT 0x4
#define IOSF_PORT_NC 0x11
-#define VLV_IOSF_DATA 0x182104
-#define VLV_IOSF_ADDR 0x182108
+#define BYT_IOSF_DATA 0x182104
+#define BYT_IOSF_ADDR 0x182108
#define PUNIT_OPCODE_REG_READ 6
#define PUNIT_OPCODE_REG_WRITE 7
@@ -4580,7 +4580,7 @@
#define GEN7_L3LOG_BASE 0xB070
#define GEN7_L3LOG_SIZE 0x80
-#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
+#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + BYT */
#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
#define GEN7_MAX_PS_THREAD_DEP (8<<12)
#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index c0d7875..338345f 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -212,10 +212,10 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
int ret;
mutex_lock(&dev_priv->rps.hw_lock);
- if (IS_VALLEYVIEW(dev_priv->dev)) {
+ if (IS_BAYTRAIL(dev_priv->dev)) {
u32 freq;
- valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &freq);
- ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
+ baytrail_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &freq);
+ ret = byt_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
} else {
ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
}
@@ -232,8 +232,8 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
int ret;
mutex_lock(&dev_priv->rps.hw_lock);
- if (IS_VALLEYVIEW(dev_priv->dev))
- ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);
+ if (IS_BAYTRAIL(dev_priv->dev))
+ ret = byt_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);
else
ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
mutex_unlock(&dev_priv->rps.hw_lock);
@@ -257,11 +257,11 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
mutex_lock(&dev_priv->rps.hw_lock);
- if (IS_VALLEYVIEW(dev_priv->dev)) {
- val = vlv_freq_opcode(dev_priv->mem_freq, val);
+ if (IS_BAYTRAIL(dev_priv->dev)) {
+ val = byt_freq_opcode(dev_priv->mem_freq, val);
- hw_max = valleyview_rps_max_freq(dev_priv);
- hw_min = valleyview_rps_min_freq(dev_priv);
+ hw_max = baytrail_rps_max_freq(dev_priv);
+ hw_min = baytrail_rps_min_freq(dev_priv);
non_oc_max = hw_max;
} else {
val /= GT_FREQUENCY_MULTIPLIER;
@@ -283,8 +283,8 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
val * GT_FREQUENCY_MULTIPLIER);
if (dev_priv->rps.cur_delay > val) {
- if (IS_VALLEYVIEW(dev_priv->dev))
- valleyview_set_rps(dev_priv->dev, val);
+ if (IS_BAYTRAIL(dev_priv->dev))
+ baytrail_set_rps(dev_priv->dev, val);
else
gen6_set_rps(dev_priv->dev, val);
}
@@ -304,8 +304,8 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
int ret;
mutex_lock(&dev_priv->rps.hw_lock);
- if (IS_VALLEYVIEW(dev_priv->dev))
- ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);
+ if (IS_BAYTRAIL(dev_priv->dev))
+ ret = byt_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);
else
ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
mutex_unlock(&dev_priv->rps.hw_lock);
@@ -329,11 +329,11 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
mutex_lock(&dev_priv->rps.hw_lock);
- if (IS_VALLEYVIEW(dev)) {
- val = vlv_freq_opcode(dev_priv->mem_freq, val);
+ if (IS_BAYTRAIL(dev)) {
+ val = byt_freq_opcode(dev_priv->mem_freq, val);
- hw_max = valleyview_rps_max_freq(dev_priv);
- hw_min = valleyview_rps_min_freq(dev_priv);
+ hw_max = baytrail_rps_max_freq(dev_priv);
+ hw_min = baytrail_rps_min_freq(dev_priv);
} else {
val /= GT_FREQUENCY_MULTIPLIER;
@@ -348,8 +348,8 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
}
if (dev_priv->rps.cur_delay < val) {
- if (IS_VALLEYVIEW(dev))
- valleyview_set_rps(dev, val);
+ if (IS_BAYTRAIL(dev))
+ baytrail_set_rps(dev, val);
else
gen6_set_rps(dev_priv->dev, val);
}
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 1b9ebf4..b42928a 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -135,7 +135,7 @@ static void intel_crt_dpms(struct drm_connector *connector, int mode)
struct drm_crtc *crtc;
int old_dpms;
- /* PCH platforms and VLV only support on/off. */
+ /* PCH platforms and BYT only support on/off. */
if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
mode = DRM_MODE_DPMS_OFF;
@@ -298,7 +298,7 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
return ret;
}
-static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
+static bool baytrail_crt_detect_hotplug(struct drm_connector *connector)
{
struct drm_device *dev = connector->dev;
struct intel_crt *crt = intel_attached_crt(connector);
@@ -327,7 +327,7 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
else
ret = false;
- DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
+ DRM_DEBUG_KMS("baytrail hotplug adpa=0x%x, result %d\n", adpa, ret);
/* FIXME: debug force function and remove */
ret = true;
@@ -354,8 +354,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
if (HAS_PCH_SPLIT(dev))
return intel_ironlake_crt_detect_hotplug(connector);
- if (IS_VALLEYVIEW(dev))
- return valleyview_crt_detect_hotplug(connector);
+ if (IS_BAYTRAIL(dev))
+ return baytrail_crt_detect_hotplug(connector);
/*
* On 4 series desktop, CRT detect sequence need to be done twice
@@ -770,8 +770,8 @@ void intel_crt_init(struct drm_device *dev)
if (HAS_PCH_SPLIT(dev))
crt->adpa_reg = PCH_ADPA;
- else if (IS_VALLEYVIEW(dev))
- crt->adpa_reg = VLV_ADPA;
+ else if (IS_BAYTRAIL(dev))
+ crt->adpa_reg = BYT_ADPA;
else
crt->adpa_reg = ADPA;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 34153e6..1333bca 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -102,7 +102,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
intel_clock_t *best_clock);
static bool
-intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
+intel_byt_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
int target, int refclk, intel_clock_t *match_clock,
intel_clock_t *best_clock);
@@ -339,7 +339,7 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
.find_pll = intel_g4x_find_best_PLL,
};
-static const intel_limit_t intel_limits_vlv_dac = {
+static const intel_limit_t intel_limits_byt_dac = {
.dot = { .min = 25000, .max = 270000 },
.vco = { .min = 4000000, .max = 6000000 },
.n = { .min = 1, .max = 7 },
@@ -350,10 +350,10 @@ static const intel_limit_t intel_limits_vlv_dac = {
.p1 = { .min = 1, .max = 3 },
.p2 = { .dot_limit = 270000,
.p2_slow = 2, .p2_fast = 20 },
- .find_pll = intel_vlv_find_best_pll,
+ .find_pll = intel_byt_find_best_pll,
};
-static const intel_limit_t intel_limits_vlv_hdmi = {
+static const intel_limit_t intel_limits_byt_hdmi = {
.dot = { .min = 25000, .max = 270000 },
.vco = { .min = 4000000, .max = 6000000 },
.n = { .min = 1, .max = 7 },
@@ -364,10 +364,10 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
.p1 = { .min = 2, .max = 3 },
.p2 = { .dot_limit = 270000,
.p2_slow = 2, .p2_fast = 20 },
- .find_pll = intel_vlv_find_best_pll,
+ .find_pll = intel_byt_find_best_pll,
};
-static const intel_limit_t intel_limits_vlv_dp = {
+static const intel_limit_t intel_limits_byt_dp = {
.dot = { .min = 25000, .max = 270000 },
.vco = { .min = 4000000, .max = 6000000 },
.n = { .min = 1, .max = 7 },
@@ -378,7 +378,7 @@ static const intel_limit_t intel_limits_vlv_dp = {
.p1 = { .min = 1, .max = 3 },
.p2 = { .dot_limit = 270000,
.p2_slow = 2, .p2_fast = 20 },
- .find_pll = intel_vlv_find_best_pll,
+ .find_pll = intel_byt_find_best_pll,
};
u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
@@ -477,13 +477,13 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
limit = &intel_limits_pineview_lvds;
else
limit = &intel_limits_pineview_sdvo;
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_BAYTRAIL(dev)) {
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
- limit = &intel_limits_vlv_dac;
+ limit = &intel_limits_byt_dac;
else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
- limit = &intel_limits_vlv_hdmi;
+ limit = &intel_limits_byt_hdmi;
else
- limit = &intel_limits_vlv_dp;
+ limit = &intel_limits_byt_dp;
} else if (!IS_GEN2(dev)) {
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
limit = &intel_limits_i9xx_lvds;
@@ -701,7 +701,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
}
static bool
-intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
+intel_byt_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
int target, int refclk, intel_clock_t *match_clock,
intel_clock_t *best_clock)
{
@@ -1150,7 +1150,7 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
int cur_pipe;
/* Planes are fixed to pipes on ILK+ */
- if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
+ if (HAS_PCH_SPLIT(dev_priv->dev) || IS_BAYTRAIL(dev_priv->dev)) {
reg = DSPCNTR(pipe);
val = I915_READ(reg);
WARN((val & DISPLAY_PLANE_ENABLE),
@@ -1177,7 +1177,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
int reg, i;
u32 val;
- if (!IS_VALLEYVIEW(dev_priv->dev))
+ if (!IS_BAYTRAIL(dev_priv->dev))
return;
/* Need to check both planes against the pipe */
@@ -1360,7 +1360,7 @@ static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
assert_pipe_disabled(dev_priv, pipe);
/* No really, not for ILK+ */
- BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
+ BUG_ON(!IS_BAYTRAIL(dev_priv->dev) && dev_priv->info->gen >= 5);
/* PLL is protected by panel, make sure we can write it */
if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
@@ -1471,7 +1471,7 @@ intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
return I915_READ(SBI_DATA);
}
-void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
+void byt_wait_port_ready(struct drm_i915_private *dev_priv, int port)
{
u32 port_mask;
@@ -3648,7 +3648,7 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
I915_WRITE(BCLRPAT(crtc->pipe), 0);
}
-static void valleyview_crtc_enable(struct drm_crtc *crtc)
+static void baytrail_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3677,7 +3677,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
if (encoder->pre_enable)
encoder->pre_enable(encoder);
- /* VLV wants encoder enabling _before_ the pipe is up. */
+ /* BYT wants encoder enabling _before_ the pipe is up. */
for_each_encoder_on_crtc(dev, crtc, encoder)
encoder->enable(encoder);
@@ -4126,13 +4126,13 @@ static int intel_crtc_compute_config(struct drm_crtc *crtc,
drm_mode_set_crtcinfo(adjusted_mode, 0);
/* Cantiga+ cannot handle modes with a hsync front porch of 0.
- * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
+ * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,byt,hsw.
*/
if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
adjusted_mode->hsync_start == adjusted_mode->hdisplay)
return -EINVAL;
- if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
+ if ((IS_G4X(dev) || IS_BAYTRAIL(dev)) && pipe_config->pipe_bpp > 10*3) {
pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
} else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
/* only a 8bpc pipe, with 6bpc dither through the panel fitter
@@ -4146,7 +4146,7 @@ static int intel_crtc_compute_config(struct drm_crtc *crtc,
return 0;
}
-static int valleyview_get_display_clock_speed(struct drm_device *dev)
+static int baytrail_get_display_clock_speed(struct drm_device *dev)
{
return 400000; /* FIXME */
}
@@ -4256,7 +4256,7 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
}
-static int vlv_get_refclk(struct drm_crtc *crtc)
+static int byt_get_refclk(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4284,8 +4284,8 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
struct drm_i915_private *dev_priv = dev->dev_private;
int refclk;
- if (IS_VALLEYVIEW(dev)) {
- refclk = vlv_get_refclk(crtc);
+ if (IS_BAYTRAIL(dev)) {
+ refclk = byt_get_refclk(crtc);
} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
refclk = dev_priv->lvds_ssc_freq * 1000;
@@ -4364,7 +4364,7 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
}
}
-static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
+static void byt_pllb_recal_opamp(struct drm_i915_private *dev_priv)
{
u32 reg_val;
@@ -4434,7 +4434,7 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc)
intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
}
-static void vlv_update_pll(struct intel_crtc *crtc)
+static void byt_update_pll(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4461,7 +4461,7 @@ static void vlv_update_pll(struct intel_crtc *crtc)
/* PLL B needs special handling */
if (pipe)
- vlv_pllb_recal_opamp(dev_priv);
+ byt_pllb_recal_opamp(dev_priv);
/* Set up Tx target for periodic Rcomp update */
intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
@@ -4533,17 +4533,17 @@ static void vlv_update_pll(struct intel_crtc *crtc)
encoder->pre_pll_enable(encoder);
/* Enable DPIO clock input */
- dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
- DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
+ dpll = DPLL_EXT_BUFFER_ENABLE_BYT | DPLL_REFA_CLK_ENABLE_BYT |
+ DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_BYT;
if (pipe)
- dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
+ dpll |= DPLL_INTEGRATED_CRI_CLK_BYT;
dpll |= DPLL_VCO_ENABLE;
I915_WRITE(DPLL(pipe), dpll);
POSTING_READ(DPLL(pipe));
udelay(150);
- if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
+ if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_BYT) == DPLL_LOCK_BYT), 1))
DRM_ERROR("DPLL %d failed to lock\n", pipe);
dpll_md = 0;
@@ -4849,7 +4849,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
}
/* only g4x and later have fancy bpc/dither controls */
- if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+ if (IS_G4X(dev) || IS_BAYTRAIL(dev)) {
pipeconf &= ~(PIPECONF_BPC_MASK |
PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
@@ -4891,7 +4891,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
else
pipeconf |= PIPECONF_PROGRESSIVE;
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_BAYTRAIL(dev)) {
if (intel_crtc->config.limited_color_range)
pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
else
@@ -4989,8 +4989,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
i8xx_update_pll(intel_crtc, adjusted_mode,
has_reduced_clock ? &reduced_clock : NULL,
num_connectors);
- else if (IS_VALLEYVIEW(dev))
- vlv_update_pll(intel_crtc);
+ else if (IS_BAYTRAIL(dev))
+ byt_update_pll(intel_crtc);
else
i9xx_update_pll(intel_crtc,
has_reduced_clock ? &reduced_clock : NULL,
@@ -4999,7 +4999,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
- if (!IS_VALLEYVIEW(dev)) {
+ if (!IS_BAYTRAIL(dev)) {
if (pipe == 0)
dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
else
@@ -8813,16 +8813,16 @@ static void intel_setup_outputs(struct drm_device *dev)
if (I915_READ(PCH_DP_D) & DP_DETECTED)
intel_dp_init(dev, PCH_DP_D, PORT_D);
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_BAYTRAIL(dev)) {
/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
- if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
- intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
+ if (I915_READ(BYT_DISPLAY_BASE + DP_C) & DP_DETECTED)
+ intel_dp_init(dev, BYT_DISPLAY_BASE + DP_C, PORT_C);
- if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
- intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
+ if (I915_READ(BYT_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
+ intel_hdmi_init(dev, BYT_DISPLAY_BASE + GEN4_HDMIB,
PORT_B);
- if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
- intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
+ if (I915_READ(BYT_DISPLAY_BASE + DP_B) & DP_DETECTED)
+ intel_dp_init(dev, BYT_DISPLAY_BASE + DP_B, PORT_B);
}
} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
bool found = false;
@@ -9033,10 +9033,10 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.crtc_disable = ironlake_crtc_disable;
dev_priv->display.off = ironlake_crtc_off;
dev_priv->display.update_plane = ironlake_update_plane;
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_BAYTRAIL(dev)) {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
- dev_priv->display.crtc_enable = valleyview_crtc_enable;
+ dev_priv->display.crtc_enable = baytrail_crtc_enable;
dev_priv->display.crtc_disable = i9xx_crtc_disable;
dev_priv->display.off = i9xx_crtc_off;
dev_priv->display.update_plane = i9xx_update_plane;
@@ -9050,9 +9050,9 @@ static void intel_init_display(struct drm_device *dev)
}
/* Returns the core display clock speed */
- if (IS_VALLEYVIEW(dev))
+ if (IS_BAYTRAIL(dev))
dev_priv->display.get_display_clock_speed =
- valleyview_get_display_clock_speed;
+ baytrail_get_display_clock_speed;
else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
dev_priv->display.get_display_clock_speed =
i945_get_display_clock_speed;
@@ -9819,7 +9819,7 @@ intel_display_capture_error_state(struct drm_device *dev)
cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
error->pipe[i].cpu_transcoder = cpu_transcoder;
- if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
+ if (INTEL_INFO(dev)->gen <= 6 || IS_BAYTRAIL(dev)) {
error->cursor[i].control = I915_READ(CURCNTR(i));
error->cursor[i].position = I915_READ(CURPOS(i));
error->cursor[i].base = I915_READ(CURBASE(i));
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 65d28cb..94adcb3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -222,8 +222,8 @@ intel_hrawclk(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t clkcfg;
- /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
- if (IS_VALLEYVIEW(dev))
+ /* There is no CLKCFG reg in Baytrail. BYT hrawclk is 200 MHz */
+ if (IS_BAYTRAIL(dev))
return 200;
clkcfg = I915_READ(CLKCFG);
@@ -255,7 +255,7 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev->dev_private;
u32 pp_stat_reg;
- pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_stat_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
return (I915_READ(pp_stat_reg) & PP_ON) != 0;
}
@@ -265,7 +265,7 @@ static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev->dev_private;
u32 pp_ctrl_reg;
- pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ pp_ctrl_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
}
@@ -279,8 +279,8 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
if (!is_edp(intel_dp))
return;
- pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
- pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ pp_stat_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_ctrl_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
WARN(1, "eDP powered off while attempting aux channel communication.\n");
@@ -328,7 +328,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
uint32_t status;
uint32_t aux_clock_divider;
int try, precharge;
- bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
+ bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_BAYTRAIL(dev);
/* dp aux is extremely sensitive to irq latency, hence request the
* lowest possible wakeup latency and so prevent the cpu from going into
@@ -347,7 +347,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
if (is_cpu_edp(intel_dp)) {
if (HAS_DDI(dev))
aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
- else if (IS_VALLEYVIEW(dev))
+ else if (IS_BAYTRAIL(dev))
aux_clock_divider = 100;
else if (IS_GEN6(dev) || IS_GEN7(dev))
aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
@@ -698,8 +698,8 @@ intel_dp_set_clock(struct intel_encoder *encoder,
pipe_config->dpll.m2 = 8;
}
pipe_config->clock_set = true;
- } else if (IS_VALLEYVIEW(dev)) {
- /* FIXME: Need to figure out optimized DP clocks for vlv. */
+ } else if (IS_BAYTRAIL(dev)) {
+ /* FIXME: Need to figure out optimized DP clocks for byt. */
}
}
@@ -894,7 +894,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
/* Split out the IBX/CPU vs CPT settings */
- if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
+ if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_BAYTRAIL(dev)) {
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
intel_dp->DP |= DP_SYNC_HS_HIGH;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -912,7 +912,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
else
intel_dp->DP |= DP_PLL_FREQ_270MHZ;
} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
- if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
+ if (!HAS_PCH_SPLIT(dev) && !IS_BAYTRAIL(dev))
intel_dp->DP |= intel_dp->color_range;
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -927,7 +927,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
if (intel_crtc->pipe == 1)
intel_dp->DP |= DP_PIPEB_SELECT;
- if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
+ if (is_cpu_edp(intel_dp) && !IS_BAYTRAIL(dev)) {
/* don't miss out required setting for eDP */
if (adjusted_mode->clock < 200000)
intel_dp->DP |= DP_PLL_FREQ_160MHZ;
@@ -938,7 +938,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
}
- if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
+ if (is_cpu_edp(intel_dp) && !IS_BAYTRAIL(dev))
ironlake_set_pll_edp(crtc, adjusted_mode->clock);
}
@@ -959,8 +959,8 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dev->dev_private;
u32 pp_stat_reg, pp_ctrl_reg;
- pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
- pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ pp_stat_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_ctrl_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
mask, value,
@@ -1004,7 +1004,7 @@ static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
u32 control;
u32 pp_ctrl_reg;
- pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ pp_ctrl_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
control = I915_READ(pp_ctrl_reg);
control &= ~PANEL_UNLOCK_MASK;
@@ -1039,8 +1039,8 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
pp = ironlake_get_pp_control(intel_dp);
pp |= EDP_FORCE_VDD;
- pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
- pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ pp_stat_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_ctrl_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
I915_WRITE(pp_ctrl_reg, pp);
POSTING_READ(pp_ctrl_reg);
@@ -1068,8 +1068,8 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
pp = ironlake_get_pp_control(intel_dp);
pp &= ~EDP_FORCE_VDD;
- pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
- pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ pp_stat_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
+ pp_ctrl_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
I915_WRITE(pp_ctrl_reg, pp);
POSTING_READ(pp_ctrl_reg);
@@ -1146,7 +1146,7 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
if (!IS_GEN5(dev))
pp |= PANEL_POWER_RESET;
- pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ pp_ctrl_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
I915_WRITE(pp_ctrl_reg, pp);
POSTING_READ(pp_ctrl_reg);
@@ -1179,7 +1179,7 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
* panels get very unhappy and cease to work. */
pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
- pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ pp_ctrl_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
I915_WRITE(pp_ctrl_reg, pp);
POSTING_READ(pp_ctrl_reg);
@@ -1212,7 +1212,7 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
pp = ironlake_get_pp_control(intel_dp);
pp |= EDP_BLC_ENABLE;
- pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ pp_ctrl_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
I915_WRITE(pp_ctrl_reg, pp);
POSTING_READ(pp_ctrl_reg);
@@ -1236,7 +1236,7 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
pp = ironlake_get_pp_control(intel_dp);
pp &= ~EDP_BLC_ENABLE;
- pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+ pp_ctrl_reg = IS_BAYTRAIL(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
I915_WRITE(pp_ctrl_reg, pp);
POSTING_READ(pp_ctrl_reg);
@@ -1335,7 +1335,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
if (!(tmp & DP_PORT_EN))
return false;
- if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
+ if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_BAYTRAIL(dev)) {
*pipe = PORT_TO_PIPE_CPT(tmp);
} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
*pipe = PORT_TO_PIPE(tmp);
@@ -1396,7 +1396,7 @@ static void intel_post_disable_dp(struct intel_encoder *encoder)
if (is_cpu_edp(intel_dp)) {
intel_dp_link_down(intel_dp);
- if (!IS_VALLEYVIEW(dev))
+ if (!IS_BAYTRAIL(dev))
ironlake_edp_pll_off(intel_dp);
}
}
@@ -1420,12 +1420,12 @@ static void intel_enable_dp(struct intel_encoder *encoder)
intel_dp_stop_link_train(intel_dp);
ironlake_edp_backlight_on(intel_dp);
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_BAYTRAIL(dev)) {
struct intel_digital_port *dport =
enc_to_dig_port(&encoder->base);
- int channel = vlv_dport_to_channel(dport);
+ int channel = byt_dport_to_channel(dport);
- vlv_wait_port_ready(dev_priv, channel);
+ byt_wait_port_ready(dev_priv, channel);
}
}
@@ -1435,14 +1435,14 @@ static void intel_pre_enable_dp(struct intel_encoder *encoder)
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
+ if (is_cpu_edp(intel_dp) && !IS_BAYTRAIL(dev))
ironlake_edp_pll_on(intel_dp);
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_BAYTRAIL(dev)) {
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
struct intel_crtc *intel_crtc =
to_intel_crtc(encoder->base.crtc);
- int port = vlv_dport_to_channel(dport);
+ int port = byt_dport_to_channel(dport);
int pipe = intel_crtc->pipe;
u32 val;
@@ -1469,9 +1469,9 @@ static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- int port = vlv_dport_to_channel(dport);
+ int port = byt_dport_to_channel(dport);
- if (!IS_VALLEYVIEW(dev))
+ if (!IS_BAYTRAIL(dev))
return;
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
@@ -1552,7 +1552,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
- if (IS_VALLEYVIEW(dev))
+ if (IS_BAYTRAIL(dev))
return DP_TRAIN_VOLTAGE_SWING_1200;
else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
return DP_TRAIN_VOLTAGE_SWING_800;
@@ -1579,7 +1579,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
default:
return DP_TRAIN_PRE_EMPHASIS_0;
}
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_BAYTRAIL(dev)) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_400:
return DP_TRAIN_PRE_EMPHASIS_9_5;
@@ -1616,7 +1616,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
}
}
-static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
+static uint32_t intel_byt_signal_levels(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1624,7 +1624,7 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
unsigned long demph_reg_value, preemph_reg_value,
uniqtranscale_reg_value;
uint8_t train_set = intel_dp->train_set[0];
- int port = vlv_dport_to_channel(dport);
+ int port = byt_dport_to_channel(dport);
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
@@ -1887,8 +1887,8 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
if (HAS_DDI(dev)) {
signal_levels = intel_hsw_signal_levels(train_set);
mask = DDI_BUF_EMP_MASK;
- } else if (IS_VALLEYVIEW(dev)) {
- signal_levels = intel_vlv_signal_levels(intel_dp);
+ } else if (IS_BAYTRAIL(dev)) {
+ signal_levels = intel_byt_signal_levels(intel_dp);
mask = 0;
} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
signal_levels = intel_gen7_edp_signal_levels(train_set);
@@ -2952,7 +2952,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
pp_div_reg = PIPEA_PP_DIVISOR;
}
- if (IS_VALLEYVIEW(dev))
+ if (IS_BAYTRAIL(dev))
port_sel = I915_READ(pp_on_reg) & 0xc0000000;
/* And finally store the new values in the power sequencer. */
@@ -3012,9 +3012,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
/*
* FIXME : We need to initialize built-in panels before external panels.
- * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
+ * For X0, DP_C is fixed as eDP. Revisit this as part of BYT eDP cleanup
*/
- if (IS_VALLEYVIEW(dev) && port == PORT_C) {
+ if (IS_BAYTRAIL(dev) && port == PORT_C) {
type = DRM_MODE_CONNECTOR_eDP;
intel_encoder->type = INTEL_OUTPUT_EDP;
} else if (port == PORT_A || is_pch_edp(intel_dp)) {
@@ -3200,7 +3200,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
intel_encoder->disable = intel_disable_dp;
intel_encoder->post_disable = intel_post_disable_dp;
intel_encoder->get_hw_state = intel_dp_get_hw_state;
- if (IS_VALLEYVIEW(dev))
+ if (IS_BAYTRAIL(dev))
intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
intel_dig_port->port = port;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4832b9e..a7ead5c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -245,7 +245,7 @@ struct intel_crtc_config {
/* Used by SDVO (and if we ever fix it, HDMI). */
unsigned pixel_multiplier;
- /* Panel fitter controls for gen2-gen4 + VLV */
+ /* Panel fitter controls for gen2-gen4 + BYT */
struct {
u32 control;
u32 pgm_ratios;
@@ -472,7 +472,7 @@ struct intel_digital_port {
};
static inline int
-vlv_dport_to_channel(struct intel_digital_port *dport)
+byt_dport_to_channel(struct intel_digital_port *dport)
{
switch (dport->port) {
case PORT_B:
@@ -663,7 +663,7 @@ intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
-extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
+extern void byt_wait_port_ready(struct drm_i915_private *dev_priv, int port);
struct intel_load_detect_pipe {
struct drm_framebuffer *release_fb;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 2b727f0..2803c3c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -249,14 +249,14 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,
POSTING_READ(reg);
}
-static void vlv_write_infoframe(struct drm_encoder *encoder,
+static void byt_write_infoframe(struct drm_encoder *encoder,
struct dip_infoframe *frame)
{
uint32_t *data = (uint32_t *)frame;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
- int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
+ int reg = BYT_TVIDEO_DIP_CTL(intel_crtc->pipe);
unsigned i, len = DIP_HEADER_SIZE + frame->len;
u32 val = I915_READ(reg);
@@ -271,12 +271,12 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
mmiowb();
for (i = 0; i < len; i += 4) {
- I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
+ I915_WRITE(BYT_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
data++;
}
/* Write every possible data byte to force correct ECC calculation. */
for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
- I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
+ I915_WRITE(BYT_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
mmiowb();
val |= g4x_infoframe_enable(frame);
@@ -530,13 +530,13 @@ static void cpt_set_infoframes(struct drm_encoder *encoder,
intel_hdmi_set_spd_infoframe(encoder);
}
-static void vlv_set_infoframes(struct drm_encoder *encoder,
+static void byt_set_infoframes(struct drm_encoder *encoder,
struct drm_display_mode *adjusted_mode)
{
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
- u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
+ u32 reg = BYT_TVIDEO_DIP_CTL(intel_crtc->pipe);
u32 val = I915_READ(reg);
assert_hdmi_port_disabled(intel_hdmi);
@@ -602,7 +602,7 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
u32 hdmi_val;
hdmi_val = SDVO_ENCODING_HDMI;
- if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
+ if (!HAS_PCH_SPLIT(dev) && !IS_BAYTRAIL(dev))
hdmi_val |= intel_hdmi->color_range;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
@@ -698,12 +698,12 @@ static void intel_enable_hdmi(struct intel_encoder *encoder)
POSTING_READ(intel_hdmi->hdmi_reg);
}
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_BAYTRAIL(dev)) {
struct intel_digital_port *dport =
enc_to_dig_port(&encoder->base);
- int channel = vlv_dport_to_channel(dport);
+ int channel = byt_dport_to_channel(dport);
- vlv_wait_port_ready(dev_priv, channel);
+ byt_wait_port_ready(dev_priv, channel);
}
}
@@ -803,7 +803,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
/*
* HDMI is either 12 or 8, so if the display lets 10bpc sneak
- * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
+ * through, clamp it down. Note that g4x/byt don't support 12bpc hdmi
* outputs. We also need to check that the higher clock still fits
* within limits.
*/
@@ -989,11 +989,11 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc =
to_intel_crtc(encoder->base.crtc);
- int port = vlv_dport_to_channel(dport);
+ int port = byt_dport_to_channel(dport);
int pipe = intel_crtc->pipe;
u32 val;
- if (!IS_VALLEYVIEW(dev))
+ if (!IS_BAYTRAIL(dev))
return;
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
@@ -1036,9 +1036,9 @@ static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- int port = vlv_dport_to_channel(dport);
+ int port = byt_dport_to_channel(dport);
- if (!IS_VALLEYVIEW(dev))
+ if (!IS_BAYTRAIL(dev))
return;
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
@@ -1068,9 +1068,9 @@ static void intel_hdmi_post_disable(struct intel_encoder *encoder)
{
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
- int port = vlv_dport_to_channel(dport);
+ int port = byt_dport_to_channel(dport);
- /* Reset lanes to avoid HDMI flicker (VLV w/a) */
+ /* Reset lanes to avoid HDMI flicker (BYT w/a) */
mutex_lock(&dev_priv->dpio_lock);
intel_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000);
intel_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060);
@@ -1151,9 +1151,9 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
BUG();
}
- if (IS_VALLEYVIEW(dev)) {
- intel_hdmi->write_infoframe = vlv_write_infoframe;
- intel_hdmi->set_infoframes = vlv_set_infoframes;
+ if (IS_BAYTRAIL(dev)) {
+ intel_hdmi->write_infoframe = byt_write_infoframe;
+ intel_hdmi->set_infoframes = byt_set_infoframes;
} else if (!HAS_PCH_SPLIT(dev)) {
intel_hdmi->write_infoframe = g4x_write_infoframe;
intel_hdmi->set_infoframes = g4x_set_infoframes;
@@ -1216,7 +1216,7 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
intel_encoder->enable = intel_enable_hdmi;
intel_encoder->disable = intel_disable_hdmi;
intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_BAYTRAIL(dev)) {
intel_encoder->pre_enable = intel_hdmi_pre_enable;
intel_encoder->pre_pll_enable = intel_hdmi_pre_pll_enable;
intel_encoder->post_disable = intel_hdmi_post_disable;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 5d24503..5906f9b 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -526,8 +526,8 @@ int intel_setup_gmbus(struct drm_device *dev)
return 0;
else if (HAS_PCH_SPLIT(dev))
dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
- else if (IS_VALLEYVIEW(dev))
- dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
+ else if (IS_BAYTRAIL(dev))
+ dev_priv->gpio_mmio_base = BYT_DISPLAY_BASE;
else
dev_priv->gpio_mmio_base = 0;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1d3a790..cb38177 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -836,16 +836,16 @@ static const struct intel_watermark_params g4x_cursor_wm_info = {
2,
G4X_FIFO_LINE_SIZE,
};
-static const struct intel_watermark_params valleyview_wm_info = {
- VALLEYVIEW_FIFO_SIZE,
- VALLEYVIEW_MAX_WM,
- VALLEYVIEW_MAX_WM,
+static const struct intel_watermark_params baytrail_wm_info = {
+ BAYTRAIL_FIFO_SIZE,
+ BAYTRAIL_MAX_WM,
+ BAYTRAIL_MAX_WM,
2,
G4X_FIFO_LINE_SIZE,
};
-static const struct intel_watermark_params valleyview_cursor_wm_info = {
+static const struct intel_watermark_params baytrail_cursor_wm_info = {
I965_CURSOR_FIFO,
- VALLEYVIEW_CURSOR_MAX_WM,
+ BAYTRAIL_CURSOR_MAX_WM,
I965_CURSOR_DFT_WM,
2,
G4X_FIFO_LINE_SIZE,
@@ -1211,7 +1211,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
display, cursor);
}
-static bool vlv_compute_drain_latency(struct drm_device *dev,
+static bool byt_compute_drain_latency(struct drm_device *dev,
int plane,
int *plane_prec_mult,
int *plane_dl,
@@ -1246,12 +1246,12 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
/*
* Update drain latency registers of memory arbiter
*
- * Valleyview SoC has a new memory arbiter and needs drain latency registers
+ * Baytrail SoC has a new memory arbiter and needs drain latency registers
* to be programmed. Each plane has a drain latency multiplier and a drain
* latency value.
*/
-static void vlv_update_drain_latency(struct drm_device *dev)
+static void byt_update_drain_latency(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int planea_prec, planea_dl, planeb_prec, planeb_dl;
@@ -1260,27 +1260,27 @@ static void vlv_update_drain_latency(struct drm_device *dev)
either 16 or 32 */
/* For plane A, Cursor A */
- if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
+ if (byt_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
&cursor_prec_mult, &cursora_dl)) {
cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
- I915_WRITE(VLV_DDL1, cursora_prec |
+ I915_WRITE(BYT_DDL1, cursora_prec |
(cursora_dl << DDL_CURSORA_SHIFT) |
planea_prec | planea_dl);
}
/* For plane B, Cursor B */
- if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
+ if (byt_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
&cursor_prec_mult, &cursorb_dl)) {
cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
- I915_WRITE(VLV_DDL2, cursorb_prec |
+ I915_WRITE(BYT_DDL2, cursorb_prec |
(cursorb_dl << DDL_CURSORB_SHIFT) |
planeb_prec | planeb_dl);
}
@@ -1288,7 +1288,7 @@ static void vlv_update_drain_latency(struct drm_device *dev)
#define single_plane_enabled(mask) is_power_of_2(mask)
-static void valleyview_update_wm(struct drm_device *dev)
+static void baytrail_update_wm(struct drm_device *dev)
{
static const int sr_latency_ns = 12000;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1297,35 +1297,35 @@ static void valleyview_update_wm(struct drm_device *dev)
int ignore_plane_sr, ignore_cursor_sr;
unsigned int enabled = 0;
- vlv_update_drain_latency(dev);
+ byt_update_drain_latency(dev);
if (g4x_compute_wm0(dev, PIPE_A,
- &valleyview_wm_info, latency_ns,
- &valleyview_cursor_wm_info, latency_ns,
+ &baytrail_wm_info, latency_ns,
+ &baytrail_cursor_wm_info, latency_ns,
&planea_wm, &cursora_wm))
enabled |= 1 << PIPE_A;
if (g4x_compute_wm0(dev, PIPE_B,
- &valleyview_wm_info, latency_ns,
- &valleyview_cursor_wm_info, latency_ns,
+ &baytrail_wm_info, latency_ns,
+ &baytrail_cursor_wm_info, latency_ns,
&planeb_wm, &cursorb_wm))
enabled |= 1 << PIPE_B;
if (single_plane_enabled(enabled) &&
g4x_compute_srwm(dev, ffs(enabled) - 1,
sr_latency_ns,
- &valleyview_wm_info,
- &valleyview_cursor_wm_info,
+ &baytrail_wm_info,
+ &baytrail_cursor_wm_info,
&plane_sr, &ignore_cursor_sr) &&
g4x_compute_srwm(dev, ffs(enabled) - 1,
2*sr_latency_ns,
- &valleyview_wm_info,
- &valleyview_cursor_wm_info,
+ &baytrail_wm_info,
+ &baytrail_cursor_wm_info,
&ignore_plane_sr, &cursor_sr)) {
- I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
+ I915_WRITE(FW_BLC_SELF_BYT, FW_CSPWRDWNEN);
} else {
- I915_WRITE(FW_BLC_SELF_VLV,
- I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
+ I915_WRITE(FW_BLC_SELF_BYT,
+ I915_READ(FW_BLC_SELF_BYT) & ~FW_CSPWRDWNEN);
plane_sr = cursor_sr = 0;
}
@@ -2479,7 +2479,7 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
trace_intel_gpu_freq_change(val * 50);
}
-void valleyview_set_rps(struct drm_device *dev, u8 val)
+void baytrail_set_rps(struct drm_device *dev, u8 val)
{
struct drm_i915_private *dev_priv = dev->dev_private;
unsigned long timeout = jiffies + msecs_to_jiffies(10);
@@ -2491,17 +2491,17 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
WARN_ON(val < dev_priv->rps.min_delay);
DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
- vlv_gpu_freq(dev_priv->mem_freq,
+ byt_gpu_freq(dev_priv->mem_freq,
dev_priv->rps.cur_delay),
- vlv_gpu_freq(dev_priv->mem_freq, val));
+ byt_gpu_freq(dev_priv->mem_freq, val));
if (val == dev_priv->rps.cur_delay)
return;
- valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+ baytrail_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
do {
- valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+ baytrail_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
if (time_after(jiffies, timeout)) {
DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
break;
@@ -2509,7 +2509,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
udelay(10);
} while (pval & 1);
- valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+ baytrail_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
if ((pval >> 8) != val)
DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
val, pval >> 8);
@@ -2521,7 +2521,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
dev_priv->rps.cur_delay = pval >> 8;
- trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
+ trace_intel_gpu_freq_change(byt_gpu_freq(dev_priv->mem_freq, val));
}
@@ -2545,7 +2545,7 @@ static void gen6_disable_rps(struct drm_device *dev)
I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
}
-static void valleyview_disable_rps(struct drm_device *dev)
+static void baytrail_disable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2805,11 +2805,11 @@ static void gen6_update_ring_freq(struct drm_device *dev)
}
}
-int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
+int baytrail_rps_max_freq(struct drm_i915_private *dev_priv)
{
u32 val, rp0;
- valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
+ baytrail_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
/* Clamp to max */
@@ -2818,31 +2818,31 @@ int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
return rp0;
}
-static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+static int baytrail_rps_rpe_freq(struct drm_i915_private *dev_priv)
{
u32 val, rpe;
- valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
+ baytrail_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
- valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
+ baytrail_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
return rpe;
}
-int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
+int baytrail_rps_min_freq(struct drm_i915_private *dev_priv)
{
u32 val;
- valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
+ baytrail_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
return val & 0xff;
}
-static void vlv_rps_timer_work(struct work_struct *work)
+static void byt_rps_timer_work(struct work_struct *work)
{
drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
- rps.vlv_work.work);
+ rps.byt_work.work);
/*
* Timer fired, we must be idle. Drop to min voltage state.
@@ -2852,11 +2852,11 @@ static void vlv_rps_timer_work(struct work_struct *work)
* min freq available.
*/
mutex_lock(&dev_priv->rps.hw_lock);
- valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
+ baytrail_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
mutex_unlock(&dev_priv->rps.hw_lock);
}
-static void valleyview_enable_rps(struct drm_device *dev)
+static void baytrail_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring;
@@ -2901,7 +2901,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_CONTROL,
GEN7_RC_CTL_TO_MODE);
- valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
+ baytrail_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
switch ((val >> 6) & 3) {
case 0:
case 1:
@@ -2920,30 +2920,30 @@ static void valleyview_enable_rps(struct drm_device *dev)
DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
DRM_DEBUG_DRIVER("current GPU freq: %d\n",
- vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
+ byt_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
dev_priv->rps.cur_delay = (val >> 8) & 0xff;
- dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
+ dev_priv->rps.max_delay = baytrail_rps_max_freq(dev_priv);
dev_priv->rps.hw_max = dev_priv->rps.max_delay;
- DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
+ DRM_DEBUG_DRIVER("max GPU freq: %d\n", byt_gpu_freq(dev_priv->mem_freq,
dev_priv->rps.max_delay));
- rpe = valleyview_rps_rpe_freq(dev_priv);
+ rpe = baytrail_rps_rpe_freq(dev_priv);
DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
- vlv_gpu_freq(dev_priv->mem_freq, rpe));
+ byt_gpu_freq(dev_priv->mem_freq, rpe));
dev_priv->rps.rpe_delay = rpe;
- val = valleyview_rps_min_freq(dev_priv);
- DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
+ val = baytrail_rps_min_freq(dev_priv);
+ DRM_DEBUG_DRIVER("min GPU freq: %d\n", byt_gpu_freq(dev_priv->mem_freq,
val));
dev_priv->rps.min_delay = val;
DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
- vlv_gpu_freq(dev_priv->mem_freq, rpe));
+ byt_gpu_freq(dev_priv->mem_freq, rpe));
- INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
+ INIT_DELAYED_WORK(&dev_priv->rps.byt_work, byt_rps_timer_work);
- valleyview_set_rps(dev_priv->dev, rpe);
+ baytrail_set_rps(dev_priv->dev, rpe);
/* requires MSI enabled */
I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
@@ -3689,11 +3689,11 @@ void intel_disable_gt_powersave(struct drm_device *dev)
} else if (INTEL_INFO(dev)->gen >= 6) {
cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
cancel_work_sync(&dev_priv->rps.work);
- if (IS_VALLEYVIEW(dev))
- cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
+ if (IS_BAYTRAIL(dev))
+ cancel_delayed_work_sync(&dev_priv->rps.byt_work);
mutex_lock(&dev_priv->rps.hw_lock);
- if (IS_VALLEYVIEW(dev))
- valleyview_disable_rps(dev);
+ if (IS_BAYTRAIL(dev))
+ baytrail_disable_rps(dev);
else
gen6_disable_rps(dev);
mutex_unlock(&dev_priv->rps.hw_lock);
@@ -3709,8 +3709,8 @@ static void intel_gen6_powersave_work(struct work_struct *work)
mutex_lock(&dev_priv->rps.hw_lock);
- if (IS_VALLEYVIEW(dev)) {
- valleyview_enable_rps(dev);
+ if (IS_BAYTRAIL(dev)) {
+ baytrail_enable_rps(dev);
} else {
gen6_enable_rps(dev);
gen6_update_ring_freq(dev);
@@ -4151,7 +4151,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
gen6_check_mch_setup(dev);
}
-static void valleyview_init_clock_gating(struct drm_device *dev)
+static void baytrail_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe;
@@ -4162,46 +4162,46 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
- /* WaDisableEarlyCull:vlv */
+ /* WaDisableEarlyCull:byt */
I915_WRITE(_3D_CHICKEN3,
_MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
- /* WaDisableBackToBackFlipFix:vlv */
+ /* WaDisableBackToBackFlipFix:byt */
I915_WRITE(IVB_CHICKEN3,
CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
CHICKEN3_DGMG_DONE_FIX_DISABLE);
- /* WaDisablePSDDualDispatchEnable:vlv */
+ /* WaDisablePSDDualDispatchEnable:byt */
I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
_MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
- /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
+ /* Apply the WaDisableRHWOOptimizationForRenderHang:byt workaround. */
I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
- /* WaApplyL3ControlAndL3ChickenMode:vlv */
+ /* WaApplyL3ControlAndL3ChickenMode:byt */
I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
- /* WaForceL3Serialization:vlv */
+ /* WaForceL3Serialization:byt */
I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
~L3SQ_URB_READ_CAM_MATCH_DISABLE);
- /* WaDisableDopClockGating:vlv */
+ /* WaDisableDopClockGating:byt */
I915_WRITE(GEN7_ROW_CHICKEN2,
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
- /* WaForceL3Serialization:vlv */
+ /* WaForceL3Serialization:byt */
I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
~L3SQ_URB_READ_CAM_MATCH_DISABLE);
- /* This is required by WaCatErrorRejectionIssue:vlv */
+ /* This is required by WaCatErrorRejectionIssue:byt */
I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
- /* WaMbcDriverBootEnable:vlv */
+ /* WaMbcDriverBootEnable:byt */
I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
GEN6_MBCTL_ENABLE_BOOT_FETCH);
@@ -4217,10 +4217,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
* but we didn't debug actual testcases to find it out.
*
* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
- * This implements the WaDisableRCZUnitClockGating:vlv workaround.
+ * This implements the WaDisableRCZUnitClockGating:byt workaround.
*
- * Also apply WaDisableVDSUnitClockGating:vlv and
- * WaDisableRCPBUnitClockGating:vlv.
+ * Also apply WaDisableVDSUnitClockGating:byt and
+ * WaDisableRCPBUnitClockGating:byt.
*/
I915_WRITE(GEN6_UCGCTL2,
GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
@@ -4242,11 +4242,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
/*
- * WaDisableVLVClockGating_VBIIssue:vlv
+ * WaDisableBYTClockGating_VBIIssue:byt
* Disable clock gating on th GCFG unit to prevent a delay
* in the reporting of vblank events.
*/
- I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
+ I915_WRITE(BYT_GUNIT_CLOCK_GATE, 0xffffffff);
/* Conservative clock gating settings for now */
I915_WRITE(0x9400, 0xffffffff);
@@ -4500,10 +4500,10 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.init_clock_gating = haswell_init_clock_gating;
} else
dev_priv->display.update_wm = NULL;
- } else if (IS_VALLEYVIEW(dev)) {
- dev_priv->display.update_wm = valleyview_update_wm;
+ } else if (IS_BAYTRAIL(dev)) {
+ dev_priv->display.update_wm = baytrail_update_wm;
dev_priv->display.init_clock_gating =
- valleyview_init_clock_gating;
+ baytrail_init_clock_gating;
} else if (IS_PINEVIEW(dev)) {
if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
dev_priv->is_ddr3,
@@ -4696,40 +4696,40 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
return ret;
}
-static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
+static void byt_force_wake_reset(struct drm_i915_private *dev_priv)
{
- I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
- /* something from same cacheline, but !FORCEWAKE_VLV */
- POSTING_READ(FORCEWAKE_ACK_VLV);
+ I915_WRITE_NOTRACE(FORCEWAKE_BYT, _MASKED_BIT_DISABLE(0xffff));
+ /* something from same cacheline, but !FORCEWAKE_BYT */
+ POSTING_READ(FORCEWAKE_ACK_BYT);
}
-static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
+static void byt_force_wake_get(struct drm_i915_private *dev_priv)
{
- if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
+ if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_BYT) & FORCEWAKE_KERNEL) == 0,
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
- I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
- I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
+ I915_WRITE_NOTRACE(FORCEWAKE_BYT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
+ I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_BYT,
_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
- if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
+ if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_BYT) & FORCEWAKE_KERNEL),
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
- if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
+ if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_BYT) &
FORCEWAKE_KERNEL),
FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
- /* WaRsForcewakeWaitTC0:vlv */
+ /* WaRsForcewakeWaitTC0:byt */
__gen6_gt_wait_for_thread_c0(dev_priv);
}
-static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
+static void byt_force_wake_put(struct drm_i915_private *dev_priv)
{
- I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
- I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
+ I915_WRITE_NOTRACE(FORCEWAKE_BYT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
+ I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_BYT,
_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
/* The below doubles as a POSTING_READ */
gen6_gt_check_fifodbg(dev_priv);
@@ -4739,8 +4739,8 @@ void intel_gt_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (IS_VALLEYVIEW(dev)) {
- vlv_force_wake_reset(dev_priv);
+ if (IS_BAYTRAIL(dev)) {
+ byt_force_wake_reset(dev_priv);
} else if (INTEL_INFO(dev)->gen >= 6) {
__gen6_gt_force_wake_reset(dev_priv);
if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
@@ -4756,9 +4756,9 @@ void intel_gt_init(struct drm_device *dev)
intel_gt_reset(dev);
- if (IS_VALLEYVIEW(dev)) {
- dev_priv->gt.force_wake_get = vlv_force_wake_get;
- dev_priv->gt.force_wake_put = vlv_force_wake_put;
+ if (IS_BAYTRAIL(dev)) {
+ dev_priv->gt.force_wake_get = byt_force_wake_get;
+ dev_priv->gt.force_wake_put = byt_force_wake_put;
} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
@@ -4817,7 +4817,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
return 0;
}
-static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
+static int byt_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
u8 addr, u32 *val)
{
u32 cmd, devfn, be, bar;
@@ -4832,19 +4832,19 @@ static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
- if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
+ if (I915_READ(BYT_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
opcode == PUNIT_OPCODE_REG_READ ?
"read" : "write");
return -EAGAIN;
}
- I915_WRITE(VLV_IOSF_ADDR, addr);
+ I915_WRITE(BYT_IOSF_ADDR, addr);
if (opcode == PUNIT_OPCODE_REG_WRITE)
- I915_WRITE(VLV_IOSF_DATA, *val);
- I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
+ I915_WRITE(BYT_IOSF_DATA, *val);
+ I915_WRITE(BYT_IOSF_DOORBELL_REQ, cmd);
- if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
+ if (wait_for((I915_READ(BYT_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
5)) {
DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
@@ -4853,31 +4853,31 @@ static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
}
if (opcode == PUNIT_OPCODE_REG_READ)
- *val = I915_READ(VLV_IOSF_DATA);
- I915_WRITE(VLV_IOSF_DATA, 0);
+ *val = I915_READ(BYT_IOSF_DATA);
+ I915_WRITE(BYT_IOSF_DATA, 0);
return 0;
}
-int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
+int baytrail_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
{
- return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ,
+ return byt_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ,
addr, val);
}
-int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
+int baytrail_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
{
- return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE,
+ return byt_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE,
addr, &val);
}
-int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
+int baytrail_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
{
- return vlv_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ,
+ return byt_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ,
addr, val);
}
-int vlv_gpu_freq(int ddr_freq, int val)
+int byt_gpu_freq(int ddr_freq, int val)
{
int mult, base;
@@ -4901,7 +4901,7 @@ int vlv_gpu_freq(int ddr_freq, int val)
return ((val - 0xbd) * mult) + base;
}
-int vlv_freq_opcode(int ddr_freq, int val)
+int byt_freq_opcode(int ddr_freq, int val)
{
int mult, base;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3d2c236..c23654d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -516,7 +516,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
* to use MI_WAIT_FOR_EVENT within the CS. It should already be
* programmed to '1' on all products.
*
- * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
+ * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,byt
*/
if (INTEL_INFO(dev)->gen >= 6)
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 19b9cb9..f333d5a 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -38,7 +38,7 @@
#include "i915_drv.h"
static void
-vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
+byt_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
uint32_t x, uint32_t y,
@@ -139,7 +139,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
}
static void
-vlv_disable_plane(struct drm_plane *dplane)
+byt_disable_plane(struct drm_plane *dplane)
{
struct drm_device *dev = dplane->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -155,7 +155,7 @@ vlv_disable_plane(struct drm_plane *dplane)
}
static int
-vlv_update_colorkey(struct drm_plane *dplane,
+byt_update_colorkey(struct drm_plane *dplane,
struct drm_intel_sprite_colorkey *key)
{
struct drm_device *dev = dplane->dev;
@@ -184,7 +184,7 @@ vlv_update_colorkey(struct drm_plane *dplane,
}
static void
-vlv_get_colorkey(struct drm_plane *dplane,
+byt_get_colorkey(struct drm_plane *dplane,
struct drm_intel_sprite_colorkey *key)
{
struct drm_device *dev = dplane->dev;
@@ -978,7 +978,7 @@ static uint32_t snb_plane_formats[] = {
DRM_FORMAT_VYUY,
};
-static uint32_t vlv_plane_formats[] = {
+static uint32_t byt_plane_formats[] = {
DRM_FORMAT_RGB565,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_ARGB8888,
@@ -1036,14 +1036,14 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
intel_plane->max_downscale = 1;
}
- if (IS_VALLEYVIEW(dev)) {
- intel_plane->update_plane = vlv_update_plane;
- intel_plane->disable_plane = vlv_disable_plane;
- intel_plane->update_colorkey = vlv_update_colorkey;
- intel_plane->get_colorkey = vlv_get_colorkey;
+ if (IS_BAYTRAIL(dev)) {
+ intel_plane->update_plane = byt_update_plane;
+ intel_plane->disable_plane = byt_disable_plane;
+ intel_plane->update_colorkey = byt_update_colorkey;
+ intel_plane->get_colorkey = byt_get_colorkey;
- plane_formats = vlv_plane_formats;
- num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
+ plane_formats = byt_plane_formats;
+ num_plane_formats = ARRAY_SIZE(byt_plane_formats);
} else {
intel_plane->update_plane = ivb_update_plane;
intel_plane->disable_plane = ivb_disable_plane;
--
1.8.2.2
