On Fri, Sep 17, 2021 at 01:52:39PM -0700, José Roberto de Souza wrote:
> Specification asks for DC_STATE_DEBUG_MASK_CORES to be set for all
> platforms that supports DMC, not only for geminilake and broxton.
According to the spec it's only required for BXT and GLK, see
Bspec 4234, 49193, 49194.
The register description is a bit vague, would need to be clarified
probably.
> While at is also taking the oportunity to simply the code.
>
> BSpec: 7402
> BSpec: 49436
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@xxxxxxxxx>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 16 +++-------------
> 1 file changed, 3 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index b0268552b2863..2dc9d632969db 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -255,20 +255,10 @@ intel_get_stepping_info(struct drm_i915_private *i915,
>
> static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> {
> - u32 val, mask;
> -
> - mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> -
> - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> - mask |= DC_STATE_DEBUG_MASK_CORES;
> -
> /* The below bit doesn't need to be cleared ever afterwards */
> - val = intel_de_read(dev_priv, DC_STATE_DEBUG);
> - if ((val & mask) != mask) {
> - val |= mask;
> - intel_de_write(dev_priv, DC_STATE_DEBUG, val);
> - intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
> - }
> + intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
> + DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
> + intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
> }
>
> /**
> --
> 2.33.0
>
