On ILK-IVB the CPU side eDP is always on port-A.
Also reduce somewhat the debug verbosity.
v2:
- reduce debug verbosity
Signed-off-by: Imre Deak <imre.deak at intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5b689b2..bcadc19 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5052,7 +5052,6 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
u32 val, final;
bool has_lvds = false;
bool has_cpu_edp = false;
- bool has_pch_edp = false;
bool has_panel = false;
bool has_ck505 = false;
bool can_ssc = false;
@@ -5067,9 +5066,7 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
break;
case INTEL_OUTPUT_EDP:
has_panel = true;
- if (intel_encoder_is_pch_edp(&encoder->base))
- has_pch_edp = true;
- else
+ if (enc_to_dig_port(&encoder->base)->port == PORT_A)
has_cpu_edp = true;
break;
}
@@ -5083,9 +5080,8 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
can_ssc = true;
}
- DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
- has_panel, has_lvds, has_pch_edp, has_cpu_edp,
- has_ck505);
+ DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
+ has_panel, has_lvds, has_ck505);
/* Ironlake: try to setup display ref clock before DPLL
* enabling. This is only under driver's control after
--
1.7.10.4
