On Fri, Sep 03, 2021 at 12:26:34AM +0530, Ayaz A Siddiqui wrote:
> From: Sreedhar Telukuntla <sreedhar.telukuntla@xxxxxxxxx>
>
> Initialize the L3CC table as part of mocs initialization to program
> LNCFCMOCSx registers so that the mocs settings are available for
> selection for subsequent memory transactions in the driver load path.
>
> Apart from the above requirement, this patch is also needed for platforms
> which does not have any renderer engine.
> We have verified that value programmed LNCFCMOCSx is retained for
> XEHP-SDV, while we lose those values for DG1/TGL.
Just FYI, I believe the difference here isn't the platform itself, but
rather GuC vs execlists. With GuC submission (currently enabled by
default on XeHP and beyond), the LNCFMOCS registers are added to the
GuC's save/restore list (in guc_mmio_regset_init()) so that they're
always saved/restored across resets without any special action by i915.
But when we're using execlists, as is the default on TGL and (for now)
DG1, the driver needs to explicitly re-write the registers after a
reset, which is what the call inside intel_mocs_init_engine() takes care
of.
You might want to clarify that slightly in the commit message, but
otherwise
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
>
> Signed-off-by: Sreedhar Telukuntla <sreedhar.telukuntla@xxxxxxxxx>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 0fdadefdabc29..df8aa761d2d7f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -481,10 +481,9 @@ static u32 l3cc_combine(u16 low, u16 high)
> 0; \
> i++)
>
> -static void init_l3cc_table(struct intel_engine_cs *engine,
> +static void init_l3cc_table(struct intel_uncore *uncore,
> const struct drm_i915_mocs_table *table)
> {
> - struct intel_uncore *uncore = engine->uncore;
> unsigned int i;
> u32 l3cc;
>
> @@ -509,7 +508,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
> init_mocs_table(engine, &table);
>
> if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
> - init_l3cc_table(engine, &table);
> + init_l3cc_table(engine->uncore, &table);
> }
>
> static u32 global_mocs_offset(void)
> @@ -536,6 +535,14 @@ void intel_mocs_init(struct intel_gt *gt)
> flags = get_mocs_settings(gt->i915, &table);
> if (flags & HAS_GLOBAL_MOCS)
> __init_mocs_table(gt->uncore, &table, global_mocs_offset());
> +
> + /*
> + * Initialize the L3CC table as part of mocs initalization to make
> + * sure the LNCFCMOCSx registers are programmed for the subsequent
> + * memory transactions including guc transactions
> + */
> + if (flags & HAS_RENDER_L3CC)
> + init_l3cc_table(gt->uncore, &table);
> }
>
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> --
> 2.26.2
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
