On Fri, May 3, 2013 at 12:30 AM, Jesse Barnes <jbarnes at virtuousgeek.org> wrote: > We can't read the pfit regs if the power well is off, so use the cached > value. > > v2: re-add lost comment (Jesse) > make sure the crtc using the fitter is actually enabled (Jesse) > > Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org> Just a quick maintainer bikeshed: For fixups I highly prefer a quick git commit citation of the regressing commit plus all the cc+reviewers of the original patch in the cc section of this one. Just so that reviewers don't miss a good chance to learn something. -Daniel > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 6504337..6be34f2 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5918,7 +5918,7 @@ static void haswell_modeset_global_resources(struct drm_device *dev) > * sequence that's not yet available. Just in case desktop eDP > * on PORT D is possible on haswell, too. */ > /* Even the eDP panel fitter is outside the always-on well. */ > - if (I915_READ(PF_WIN_SZ(crtc->pipe))) > + if (crtc->config.pch_pfit.size && crtc->base.enabled) > enable = true; > } > > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
