On Fri, Aug 13, 2021 at 02:51:49PM +0300, Jani Nikula wrote:
> Needed in the future.
>
> Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++++++++++---------
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index e932fd0fe7e2..8cf5d1572ee0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1371,7 +1371,8 @@ static int translate_signal_level(struct intel_dp *intel_dp,
> return 0;
> }
>
> -static int intel_ddi_dp_level(struct intel_dp *intel_dp)
> +static int intel_ddi_dp_level(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> {
> u8 train_set = intel_dp->train_set[0];
> u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> @@ -1385,7 +1386,7 @@ dg2_set_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> - int level = intel_ddi_dp_level(intel_dp);
> + int level = intel_ddi_dp_level(intel_dp, crtc_state);
>
> intel_snps_phy_ddi_vswing_sequence(encoder, level);
> }
> @@ -1395,7 +1396,7 @@ tgl_set_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> - int level = intel_ddi_dp_level(intel_dp);
> + int level = intel_ddi_dp_level(intel_dp, crtc_state);
>
> tgl_ddi_vswing_sequence(encoder, crtc_state, level);
> }
> @@ -1405,7 +1406,7 @@ icl_set_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> - int level = intel_ddi_dp_level(intel_dp);
> + int level = intel_ddi_dp_level(intel_dp, crtc_state);
>
> icl_ddi_vswing_sequence(encoder, crtc_state, level);
> }
> @@ -1415,7 +1416,7 @@ bxt_set_signal_levels(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> - int level = intel_ddi_dp_level(intel_dp);
> + int level = intel_ddi_dp_level(intel_dp, crtc_state);
>
> bxt_ddi_vswing_sequence(encoder, crtc_state, level);
> }
> @@ -1426,7 +1427,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp,
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - int level = intel_ddi_dp_level(intel_dp);
> + int level = intel_ddi_dp_level(intel_dp, crtc_state);
> enum port port = encoder->port;
> u32 signal_levels;
>
> @@ -2328,7 +2329,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
> enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> - int level = intel_ddi_dp_level(intel_dp);
> + int level = intel_ddi_dp_level(intel_dp, crtc_state);
>
> intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> crtc_state->lane_count);
> @@ -2441,7 +2442,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> - int level = intel_ddi_dp_level(intel_dp);
> + int level = intel_ddi_dp_level(intel_dp, crtc_state);
>
> intel_dp_set_link_params(intel_dp,
> crtc_state->port_clock,
> @@ -2584,7 +2585,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> enum phy phy = intel_port_to_phy(dev_priv, port);
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> - int level = intel_ddi_dp_level(intel_dp);
> + int level = intel_ddi_dp_level(intel_dp, crtc_state);
>
> if (DISPLAY_VER(dev_priv) < 11)
> drm_WARN_ON(&dev_priv->drm,
> --
> 2.20.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
