DSI driver should have its own implementation to toggle
gpio pins based on GPIO info coming from VBT sequences.
v2: Remove redundant ICP_PP_CONTROL() define.
Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
Cc: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
Cc: Cooper Chiou <cooper.chiou@xxxxxxxxx>
Cc: William Tseng <william.tseng@xxxxxxxxx>
Signed-off-by: Lee Shawn C <shawn.c.lee@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 44 +++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index cc93e045a425..57676a5e560c 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -43,6 +43,7 @@
#include "intel_display_types.h"
#include "intel_dsi.h"
#include "intel_sideband.h"
+#include "intel_de.h"
#define MIPI_TRANSFER_MODE_SHIFT 0
#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
@@ -354,7 +355,48 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
static void icl_exec_gpio(struct drm_i915_private *dev_priv,
u8 gpio_source, u8 gpio_index, bool value)
{
- drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
+ u32 val;
+
+ switch (gpio_index) {
+ case ICL_GPIO_L_VDDEN_1:
+ val = intel_de_read(dev_priv, PP_CONTROL(0));
+ if (value)
+ val |= PANEL_POWER_ON;
+ else
+ val &= ~PANEL_POWER_ON;
+ intel_de_write(dev_priv, PP_CONTROL(0), val);
+ break;
+ case ICL_GPIO_L_BKLTEN_1:
+ val = intel_de_read(dev_priv, PP_CONTROL(0));
+ if (value)
+ val |= EDP_BLC_ENABLE;
+ else
+ val &= ~EDP_BLC_ENABLE;
+ intel_de_write(dev_priv, PP_CONTROL(0), val);
+ break;
+ case ICL_GPIO_DDPA_CTRLCLK_1:
+ val = intel_de_read(dev_priv, GPIO(1));
+ if (value)
+ val |= GPIO_CLOCK_VAL_OUT;
+ else
+ val &= ~GPIO_CLOCK_VAL_OUT;
+ val |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK;
+ intel_de_write(dev_priv, GPIO(1), val);
+ break;
+ case ICL_GPIO_DDPA_CTRLDATA_1:
+ val = intel_de_read(dev_priv, GPIO(1));
+ if (value)
+ val |= GPIO_DATA_VAL_OUT;
+ else
+ val &= ~GPIO_DATA_VAL_OUT;
+ val |= GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | GPIO_DATA_VAL_MASK;
+ intel_de_write(dev_priv, GPIO(1), val);
+ break;
+ default:
+ /* TODO: Add support for remaining GPIOs */
+ DRM_ERROR("Invalid GPIO number (%d) from VBT\n", gpio_index);
+ break;
+ }
}
static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
--
2.17.1
