✗ Fi.CI.IGT: failure for drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled

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Title: Project List - Patchwork
Patch Details
Series:drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled
URL:https://patchwork.freedesktop.org/series/93318/
State:failure
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20762/index.html

CI Bug Log - changes from CI_DRM_10440_full -> Patchwork_20762_full

Summary

FAILURE

Serious unknown changes coming with Patchwork_20762_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20762_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_20762_full:

IGT changes

Possible regressions

Known issues

Here are the changes found in Patchwork_20762_full that come from known issues:

IGT changes

Issues hit

Possible fixes

Warnings


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