On Wed, Jul 28, 2021 at 06:05:57PM -0700, Matt Roper wrote:
> On Wed, Jul 28, 2021 at 04:34:11PM -0700, Matt Roper wrote:
> > The register offset for SFC_DONE was missing a '0' at the end, causing
> > us to read from a non-existent register address. We only use this
> > register in error state dumps so the mistake hasn't caused any real
> > problems, but fixing it will hopefully make the error state dumps a bit
> > more useful for debugging.
> >
> > Fixes: e50dbdbfd9fb ("drm/i915/tgl: Add SFC instdone to error state")
> > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
> > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
>
> Hmm, actually on a closer look it appears this register may have been
> removed completely from media version 12. It will return in media
> version 13 at this offset, but for now I guess we should just drop it
> completely.
Nevermind; this register is still there on media version 12 (bspec
48109). The current register offset in the code is incorrect, so this
patch is indeed valid.
Matt
>
>
> Matt
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 70eed4fe3fe3..49dd5e75429e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -430,7 +430,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> > #define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1)
> > #define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0)
> >
> > -#define GEN12_SFC_DONE(n) _MMIO(0x1cc00 + (n) * 0x100)
> > +#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
> > #define GEN12_SFC_DONE_MAX 4
> >
> > #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
> > --
> > 2.25.4
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
