> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@xxxxxxxxx>
> Sent: Thursday, July 29, 2021 11:01 PM
> To: Roper, Matthew D <matthew.d.roper@xxxxxxxxx>
> Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; Siddiqui, Ayaz A
> <ayaz.siddiqui@xxxxxxxxx>; Daniel Vetter <daniel.vetter@xxxxxxxx>
> Subject: Re: [PATCH v4 12/18] drm/i915/xehpsdv: Define MOCS
> table for XeHP SDV
>
> On Thu, Jul 29, 2021 at 10:00:02AM -0700, Matt Roper wrote:
> >From: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> >
> >Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a
> >dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to
> >memory for L3 destined transaction" and L3_LKP to "enable Lookup for
> >uncacheable accesses".
> >
> >Bspec: 45101
> >Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
> >Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> >Signed-off-by: Stuart Summers <stuart.summers@xxxxxxxxx>
> >Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
>
> +Ayaz, +Daniel
>
> I think this can't land as is since we risk forgetting additional changes that we
> will have to do. We already made the mistake once of forgetting MOCS
> changes.
>
> There are some patches to initialize unused MOCS entries and similar that
> should have been sent already to upstream. Ayaz, what's the state of those
> patches?
There are two section of patches .
1. Programming to CMD_CCTL for with UC this patch should sent for upstream.
I'll share the patches for CMD_CCTL programming.
2. Programming of unused/unspecified MOCS index to WB, we observed some
regression on media use cases. So we decided to delay upstreaming of
those patches till MOCS programming are fixed in UMDs.
Regards
-Ayaz
>
> Lucas De Marchi
>
> >---
> > drivers/gpu/drm/i915/gt/intel_mocs.c | 33
> +++++++++++++++++++++++++++-
> > 1 file changed, 32 insertions(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> >b/drivers/gpu/drm/i915/gt/intel_mocs.c
> >index 17848807f111..0c9d0b936c20 100644
> >--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> >+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> >@@ -40,6 +40,8 @@ struct drm_i915_mocs_table {
> > #define L3_ESC(value) ((value) << 0)
> > #define L3_SCC(value) ((value) << 1)
> > #define _L3_CACHEABILITY(value) ((value) << 4)
> >+#define L3_GLBGO(value) ((value) << 6)
> >+#define L3_LKUP(value) ((value) << 7)
> >
> > /* Helper defines */
> > #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but
> configured. */
> >@@ -314,6 +316,31 @@ static const struct drm_i915_mocs_entry
> dg1_mocs_table[] = {
> > MOCS_ENTRY(63, 0, L3_1_UC),
> > };
> >
> >+static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = {
> >+ /* wa_1608975824 */
> >+ MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)),
> >+
> >+ /* UC - Coherent; GO:L3 */
> >+ MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)),
> >+ /* UC - Coherent; GO:Memory */
> >+ MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
> >+ /* UC - Non-Coherent; GO:Memory */
> >+ MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)),
> >+ /* UC - Non-Coherent; GO:L3 */
> >+ MOCS_ENTRY(4, 0, L3_1_UC),
> >+
> >+ /* WB */
> >+ MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)),
> >+
> >+ /* HW Reserved - SW program but never use. */
> >+ MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)),
> >+ MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)),
> >+ MOCS_ENTRY(60, 0, L3_1_UC),
> >+ MOCS_ENTRY(61, 0, L3_1_UC),
> >+ MOCS_ENTRY(62, 0, L3_1_UC),
> >+ MOCS_ENTRY(63, 0, L3_1_UC),
> >+};
> >+
> > enum {
> > HAS_GLOBAL_MOCS = BIT(0),
> > HAS_ENGINE_MOCS = BIT(1),
> >@@ -340,7 +367,11 @@ static unsigned int get_mocs_settings(const struct
> >drm_i915_private *i915, {
> > unsigned int flags;
> >
> >- if (IS_DG1(i915)) {
> >+ if (IS_XEHPSDV(i915)) {
> >+ table->size = ARRAY_SIZE(xehpsdv_mocs_table);
> >+ table->table = xehpsdv_mocs_table;
> >+ table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> >+ } else if (IS_DG1(i915)) {
> > table->size = ARRAY_SIZE(dg1_mocs_table);
> > table->table = dg1_mocs_table;
> > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> >--
> >2.25.4
> >
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> >Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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