On Fri, 2013-04-19 at 11:24 +0200, Daniel Vetter wrote: > Totally untested due to lack of screens supporting more than 8bpc. But > now we should have closed all holes in our bpp handling, so this > should be safe. The last missing piece was 10bpc support for g4x/vlv, > since we directly use the pipe bpp to feed the display link (and > anyway, only the cpt has any means to have a pipe bpp != the display > link bpp). > > Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch> Reviewed-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 1ac7235..50a9d9f 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -744,7 +744,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, > > /* Walk through all bpp values. Luckily they're all nicely spaced with 2 > * bpc in between. */ > - bpp = min_t(int, 8*3, pipe_config->pipe_bpp); > + bpp = pipe_config->pipe_bpp; > > /* eDP panels are really fickle, try to enfore the bpp the firmware > * recomments. This means we'll up-dither 16bpp framebuffers on
