✓ Fi.CI.BAT: success for drm/i915/adlp: Add workaround to disable CMTG clock gating

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Title: Project List - Patchwork
Patch Details
Series:drm/i915/adlp: Add workaround to disable CMTG clock gating
URL:https://patchwork.freedesktop.org/series/93067/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/index.html

CI Bug Log - changes from CI_DRM_10404 -> Patchwork_20716

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/index.html

Known issues

Here are the changes found in Patchwork_20716 that come from known issues:

IGT changes

Issues hit

Participating hosts (40 -> 35)

Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-jsl-1 fi-bdw-samus

Build changes

CI-20190529: 20190529
CI_DRM_10404: 371bd54db63fdd99356a1a3d0fdc9b76616eddcb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6153: a5dffe7499a2f7189718ddf1ccf49060b7c1529d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20716: 9cf8974d9e837f95ddbd9fef2411c699d619d24d @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

9cf8974d9e83 drm/i915/adlp: Add workaround to disable CMTG clock gating

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