Re: [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC

["Belgaumkar, Vinay" <vinay.belgaumkar@xxxxxxxxx>]

On 7/21/2021 11:13 AM, Michal Wajdeczko wrote:
> On 21.07.2021 18:11, Vinay Belgaumkar wrote:
> > Update the get/set min/max freq hooks to work for
> > SLPC case as well. Consolidate helpers for requested/min/max
> > frequency get/set to intel_rps where the proper action can
> > be taken depending on whether slpc is enabled.
>
> s/slpc/SLPC

ok.

> > v2: Add wrappers for getting rp0/1/n frequencies, update
> > softlimits in set min/max slpc functions. Also check for
> > boundary conditions before setting them.
> >
> > v3: Address review comments (Michal W)
> >
> > Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@xxxxxxxxx>
> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx>
> > Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@xxxxxxxxx>
> > ---
> >   drivers/gpu/drm/i915/gt/intel_rps.c         | 165 ++++++++++++++++++++
> >   drivers/gpu/drm/i915/gt/intel_rps.h         |  11 ++
> >   drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c |  14 ++
> >   drivers/gpu/drm/i915/i915_pmu.c             |   2 +-
> >   drivers/gpu/drm/i915/i915_reg.h             |   2 +
> >   drivers/gpu/drm/i915/i915_sysfs.c           |  77 ++-------
> >   6 files changed, 207 insertions(+), 64 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> > index e858eeb2c59d..48d4147165a9 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > @@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps *rps)
> >   	return rps_to_gt(rps)->uncore;
> >   }
> >   
> > +static struct intel_guc_slpc *rps_to_slpc(struct intel_rps *rps)
> > +{
> > +	struct intel_gt *gt = rps_to_gt(rps);
> > +
> > +	return &gt->uc.guc.slpc;
> > +}
> > +
> >   static bool rps_uses_slpc(struct intel_rps *rps)
> >   {
> >   	struct intel_gt *gt = rps_to_gt(rps);
> > @@ -1960,6 +1967,164 @@ u32 intel_rps_read_actual_frequency(struct intel_rps *rps)
> >   	return freq;
> >   }
> >   
> > +u32 intel_rps_read_punit_req(struct intel_rps *rps)
> > +{
> > +	struct intel_uncore *uncore = rps_to_uncore(rps);
> > +
> > +	return intel_uncore_read(uncore, GEN6_RPNSWREQ);
> > +}
> > +
> > +u32 intel_rps_get_req(struct intel_rps *rps, u32 pureq)
> > +{
> > +	u32 req = pureq >> GEN9_SW_REQ_UNSLICE_RATIO_SHIFT;
> > +
> > +	return req;
> > +}
> > +
> > +u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps)
> > +{
> > +	u32 freq = intel_rps_get_req(rps, intel_rps_read_punit_req(rps));
> > +
> > +	return intel_gpu_freq(rps, freq);
> > +}
> > +
> > +u32 intel_rps_get_requested_frequency(struct intel_rps *rps)
> > +{
> > +	if (rps_uses_slpc(rps))
> > +		return intel_rps_read_punit_req_frequency(rps);
> > +	else
> > +		return intel_gpu_freq(rps, rps->cur_freq);
> > +}
> > +
> > +u32 intel_rps_get_max_frequency(struct intel_rps *rps)
> > +{
> > +	struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> > +
> > +	if (rps_uses_slpc(rps))
> > +		return slpc->max_freq_softlimit;
> > +	else
> > +		return intel_gpu_freq(rps, rps->max_freq_softlimit);
> > +}
> > +
> > +u32 intel_rps_get_rp0_frequency(struct intel_rps *rps)
> > +{
> > +	struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> > +
> > +	if (rps_uses_slpc(rps))
> > +		return slpc->rp0_freq;
> > +	else
> > +		return intel_gpu_freq(rps, rps->rp0_freq);
> > +}
> > +
> > +u32 intel_rps_get_rp1_frequency(struct intel_rps *rps)
> > +{
> > +	struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> > +
> > +	if (rps_uses_slpc(rps))
> > +		return slpc->rp1_freq;
> > +	else
> > +		return intel_gpu_freq(rps, rps->rp1_freq);
> > +}
> > +
> > +u32 intel_rps_get_rpn_frequency(struct intel_rps *rps)
> > +{
> > +	struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> > +
> > +	if (rps_uses_slpc(rps))
> > +		return slpc->min_freq;
> > +	else
> > +		return intel_gpu_freq(rps, rps->min_freq);
> > +}
> > +
> > +int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val)
> > +{
> > +	struct drm_i915_private *i915 = rps_to_i915(rps);
> > +	struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> > +	int ret = 0;
> > +
> > +	if (rps_uses_slpc(rps))
> > +		return intel_guc_slpc_set_max_freq(slpc, val);
> > +
> > +	mutex_lock(&rps->lock);
> > +
> > +	val = intel_freq_opcode(rps, val);
> > +	if (val < rps->min_freq ||
> > +	    val > rps->max_freq ||
> > +	    val < rps->min_freq_softlimit) {
> > +		ret = -EINVAL;
> > +		goto unlock;
> > +	}
> > +
> > +	if (val > rps->rp0_freq)
> > +		drm_dbg(&i915->drm, "User requested overclocking to %d\n",
> > +			  intel_gpu_freq(rps, val));
> > +
> > +	rps->max_freq_softlimit = val;
> > +
> > +	val = clamp_t(int, rps->cur_freq,
> > +		      rps->min_freq_softlimit,
> > +		      rps->max_freq_softlimit);
> > +
> > +	/*
> > +	 * We still need *_set_rps to process the new max_delay and
> > +	 * update the interrupt limits and PMINTRMSK even though
> > +	 * frequency request may be unchanged.
> > +	 */
> > +	intel_rps_set(rps, val);
> > +
> > +unlock:
> > +	mutex_unlock(&rps->lock);
> > +
> > +	return ret;
> > +}
> > +
> > +u32 intel_rps_get_min_frequency(struct intel_rps *rps)
> > +{
> > +	struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> > +
> > +	if (rps_uses_slpc(rps))
> > +		return slpc->min_freq_softlimit;
> > +	else
> > +		return intel_gpu_freq(rps, rps->min_freq_softlimit);
> > +}
> > +
> > +int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val)
> > +{
> > +	struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> > +	int ret = 0;
> > +
> > +	if (rps_uses_slpc(rps))
> > +		return intel_guc_slpc_set_min_freq(slpc, val);
> > +
> > +	mutex_lock(&rps->lock);
> > +
> > +	val = intel_freq_opcode(rps, val);
> > +	if (val < rps->min_freq ||
> > +	    val > rps->max_freq ||
> > +	    val > rps->max_freq_softlimit) {
> > +		ret = -EINVAL;
> > +		goto unlock;
> > +	}
> > +
> > +	rps->min_freq_softlimit = val;
> > +
> > +	val = clamp_t(int, rps->cur_freq,
> > +		      rps->min_freq_softlimit,
> > +		      rps->max_freq_softlimit);
> > +
> > +	/*
> > +	 * We still need *_set_rps to process the new min_delay and
> > +	 * update the interrupt limits and PMINTRMSK even though
> > +	 * frequency request may be unchanged.
> > +	 */
> > +	intel_rps_set(rps, val);
> > +
> > +unlock:
> > +	mutex_unlock(&rps->lock);
> > +
> > +	return ret;
> > +}
> > +
> >   /* External interface for intel_ips.ko */
> >   
> >   static struct drm_i915_private __rcu *ips_mchdev;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
> > index 1d2cfc98b510..6a66690dfb0f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rps.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_rps.h
> > @@ -31,6 +31,17 @@ int intel_gpu_freq(struct intel_rps *rps, int val);
> >   int intel_freq_opcode(struct intel_rps *rps, int val);
> >   u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat1);
> >   u32 intel_rps_read_actual_frequency(struct intel_rps *rps);
> > +u32 intel_rps_get_requested_frequency(struct intel_rps *rps);
> > +u32 intel_rps_get_min_frequency(struct intel_rps *rps);
> > +int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val);
> > +u32 intel_rps_get_max_frequency(struct intel_rps *rps);
> > +int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val);
> > +u32 intel_rps_get_rp0_frequency(struct intel_rps *rps);
> > +u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
> > +u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
> > +u32 intel_rps_read_punit_req(struct intel_rps *rps);
> > +u32 intel_rps_get_req(struct intel_rps *rps, u32 pureq);
> > +u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
> >   
> >   void gen5_rps_irq_handler(struct intel_rps *rps);
> >   void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> > index 134c57ca10b7..05d8870ec6da 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> > @@ -301,6 +301,11 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
> >   	struct drm_i915_private *i915 = slpc_to_i915(slpc);
> >   	intel_wakeref_t wakeref;
> >   
> > +	if ((val < slpc->min_freq) ||
> > +	    (val > slpc->rp0_freq) ||
> > +	    (val < slpc->min_freq_softlimit))
> > +		return -EINVAL;
> > +
> >   	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> >   		ret = slpc_set_param(slpc,
> >   			       SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
> > @@ -313,6 +318,8 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
> >   		}
> >   	}
> >   
> > +	slpc->max_freq_softlimit = val;
> > +
> >   	return ret;
> >   }
> >   
> > @@ -359,6 +366,11 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
> >   	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> >   	intel_wakeref_t wakeref;
> >   
> > +	if ((val < slpc->min_freq) ||
> > +	    (val > slpc->rp0_freq) ||
> > +	    (val > slpc->max_freq_softlimit))
> > +		return -EINVAL;
> > +
> >   	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> >   		ret = slpc_set_param(slpc,
> >   			       SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
> > @@ -371,6 +383,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
> >   		}
> >   	}
> >   
> > +	slpc->min_freq_softlimit = val;
> > +
> >   	return ret;
> >   }
> >   
> > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> > index 34d37d46a126..a896bec18255 100644
> > --- a/drivers/gpu/drm/i915/i915_pmu.c
> > +++ b/drivers/gpu/drm/i915/i915_pmu.c
> > @@ -407,7 +407,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)
> >   
> >   	if (pmu->enable & config_mask(I915_PMU_REQUESTED_FREQUENCY)) {
> >   		add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_REQ],
> > -				intel_gpu_freq(rps, rps->cur_freq),
> > +				intel_rps_get_requested_frequency(rps),
> >   				period_ns / 1000);
> >   	}
> >   
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 92392c1da0e6..a5d893625736 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9198,6 +9198,8 @@ enum {
> >   #define   GEN9_FREQUENCY(x)			((x) << 23)
> >   #define   GEN6_OFFSET(x)			((x) << 19)
> >   #define   GEN6_AGGRESSIVE_TURBO			(0 << 15)
> > +#define   GEN9_SW_REQ_UNSLICE_RATIO_SHIFT 	23
> > +
> >   #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
> >   #define GEN6_RC_CONTROL				_MMIO(0xA090)
> >   #define   GEN6_RC_CTL_RC6pp_ENABLE		(1 << 16)
> > diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> > index 873bf996ceb5..346646a0b43b 100644
> > --- a/drivers/gpu/drm/i915/i915_sysfs.c
> > +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> > @@ -272,7 +272,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
> >   	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
> >   	struct intel_rps *rps = &i915->gt.rps;
> >   
> > -	return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->cur_freq));
> > +	return sysfs_emit(buf, "%d\n", intel_rps_get_requested_frequency(rps));
> >   }
> >   
> >   static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
> > @@ -326,9 +326,10 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
> >   static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
> >   {
> >   	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> > -	struct intel_rps *rps = &dev_priv->gt.rps;
> > +	struct intel_gt *gt = &dev_priv->gt;
> > +	struct intel_rps *rps = &gt->rps;
> >   
> > -	return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->max_freq_softlimit));
> > +	return sysfs_emit(buf, "%d\n", intel_rps_get_max_frequency(rps));
> >   }
> >   
> >   static ssize_t gt_max_freq_mhz_store(struct device *kdev,
> > @@ -336,7 +337,8 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
> >   				     const char *buf, size_t count)
> >   {
> >   	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> > -	struct intel_rps *rps = &dev_priv->gt.rps;
> > +	struct intel_gt *gt = &dev_priv->gt;
> > +	struct intel_rps *rps = &gt->rps;
> >   	ssize_t ret;
> >   	u32 val;
> >   
> > @@ -344,35 +346,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
> >   	if (ret)
> >   		return ret;
> >   
> > -	mutex_lock(&rps->lock);
> > -
> > -	val = intel_freq_opcode(rps, val);
> > -	if (val < rps->min_freq ||
> > -	    val > rps->max_freq ||
> > -	    val < rps->min_freq_softlimit) {
> > -		ret = -EINVAL;
> > -		goto unlock;
> > -	}
> > -
> > -	if (val > rps->rp0_freq)
> > -		DRM_DEBUG("User requested overclocking to %d\n",
> > -			  intel_gpu_freq(rps, val));
> > -
> > -	rps->max_freq_softlimit = val;
> > -
> > -	val = clamp_t(int, rps->cur_freq,
> > -		      rps->min_freq_softlimit,
> > -		      rps->max_freq_softlimit);
> > -
> > -	/*
> > -	 * We still need *_set_rps to process the new max_delay and
> > -	 * update the interrupt limits and PMINTRMSK even though
> > -	 * frequency request may be unchanged.
> > -	 */
> > -	intel_rps_set(rps, val);
> > -
> > -unlock:
> > -	mutex_unlock(&rps->lock);
> > +	ret = intel_rps_set_max_frequency(rps, val);
> >   
> >   	return ret ?: count;
> >   }
> > @@ -380,9 +354,10 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
> >   static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
> >   {
> >   	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> > -	struct intel_rps *rps = &dev_priv->gt.rps;
> > +	struct intel_gt *gt = &dev_priv->gt;
> > +	struct intel_rps *rps = &gt->rps;
> >   
> > -	return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->min_freq_softlimit));
> > +	return sysfs_emit(buf, "%d\n", intel_rps_get_min_frequency(rps));
> >   }
> >   
> >   static ssize_t gt_min_freq_mhz_store(struct device *kdev,
> > @@ -398,31 +373,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
> >   	if (ret)
> >   		return ret;
> >   
> > -	mutex_lock(&rps->lock);
> > -
> > -	val = intel_freq_opcode(rps, val);
> > -	if (val < rps->min_freq ||
> > -	    val > rps->max_freq ||
> > -	    val > rps->max_freq_softlimit) {
> > -		ret = -EINVAL;
> > -		goto unlock;
> > -	}
> > -
> > -	rps->min_freq_softlimit = val;
> > -
> > -	val = clamp_t(int, rps->cur_freq,
> > -		      rps->min_freq_softlimit,
> > -		      rps->max_freq_softlimit);
> > -
> > -	/*
> > -	 * We still need *_set_rps to process the new min_delay and
> > -	 * update the interrupt limits and PMINTRMSK even though
> > -	 * frequency request may be unchanged.
> > -	 */
> > -	intel_rps_set(rps, val);
> > -
> > -unlock:
> > -	mutex_unlock(&rps->lock);
> > +	ret = intel_rps_set_min_frequency(rps, val);
> >   
> >   	return ret ?: count;
> >   }
> > @@ -448,11 +399,11 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
> >   	u32 val;
> >   
> >   	if (attr == &dev_attr_gt_RP0_freq_mhz)
> > -		val = intel_gpu_freq(rps, rps->rp0_freq);
> > +		val = intel_rps_get_rp0_frequency(rps);
> >   	else if (attr == &dev_attr_gt_RP1_freq_mhz)
> > -		val = intel_gpu_freq(rps, rps->rp1_freq);
> > +		val = intel_rps_get_rp1_frequency(rps);
> >   	else if (attr == &dev_attr_gt_RPn_freq_mhz)
> > -		val = intel_gpu_freq(rps, rps->min_freq);
> > +		val = intel_rps_get_rpn_frequency(rps);
> >   	else
> >   		BUG();
> >   
>
> LGTM, but likely you will want someone who is more familiar with RPS to
> give r-b, from my side, with typo fixed, this is:

Thanks,
Vinay.
> Acked-by: Michal Wajdeczko <michal.wajdeczko@xxxxxxxxx>
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