> -----Original Message----- > From: Lee, Shawn C <shawn.c.lee@xxxxxxxxx> > Sent: Friday, July 23, 2021 12:36 PM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>; ville.syrjala@xxxxxxxxxxxxxxx; > Kulkarni, Vandita <vandita.kulkarni@xxxxxxxxx>; Chiou, Cooper > <cooper.chiou@xxxxxxxxx>; Tseng, William <william.tseng@xxxxxxxxx>; Lee, > Shawn C <shawn.c.lee@xxxxxxxxx>; Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> > Subject: [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled > > VDSC engine can process only 1 pixel per Cd clock. In case VDSC is used and > max slice count == 1, max supported pixel clock should be 100% of CD clock. > Then do min_cdclk and pixel clock comparison to get proper min cdclk. > > v2: > - Check for dsc enable and slice count ==1 then allow to > double confirm min cdclk value. LGTM, Reviewed-by: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx> > > Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> > Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> > Cc: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx> > Cc: Cooper Chiou <cooper.chiou@xxxxxxxxx> > Cc: William Tseng <william.tseng@xxxxxxxxx> > Signed-off-by: Lee Shawn C <shawn.c.lee@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 71067a62264d..3e09f6370d27 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2159,6 +2159,16 @@ int intel_crtc_compute_min_cdclk(const struct > intel_crtc_state *crtc_state) > /* Account for additional needs from the planes */ > min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); > > + /* > + * VDSC engine can process only 1 pixel per Cd clock. > + * In case VDSC is used and max slice count == 1, > + * max supported pixel clock should be 100% of CD clock. > + * Then do min_cdclk and pixel clock comparison to get cdclk. > + */ > + if (crtc_state->dsc.compression_enable && > + crtc_state->dsc.slice_count == 1) > + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); > + > /* > * HACK. Currently for TGL platforms we calculate > * min_cdclk initially based on pixel_rate divided > -- > 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
