✓ Fi.CI.BAT: success for CI pass for reviewed Xe_HP SDV and DG2 patches

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Title: Project List - Patchwork
Patch Details
Series:CI pass for reviewed Xe_HP SDV and DG2 patches
URL:https://patchwork.freedesktop.org/series/92853/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20673/index.html

CI Bug Log - changes from CI_DRM_10367 -> Patchwork_20673

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20673/index.html

Known issues

Here are the changes found in Patchwork_20673 that come from known issues:

IGT changes

Issues hit

Possible fixes

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (38 -> 35)

Missing (3): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u

Build changes

CI-20190529: 20190529
CI_DRM_10367: 598494d0149b67545593dfb1b5fa60278907749e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6146: 6caef22e4aafed275771f564d4ea4cab09896ebc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20673: 7704c9aa289a8f387a4ac8a18707cedb6f4ad6fa @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

7704c9aa289a drm/i915/dg2: DG2 has fixed memory bandwidth
358ea009b220 drm/i915/dg2: Don't read DRAM info
adb51870fc17 drm/i915/dg2: Don't program BW_BUDDY registers
4d664ff3d52d drm/i915/dg2: Add dbuf programming
f8744c6d424a drm/i915/dg2: Setup display outputs
ca6cdb06bc87 drm/i915/dg2: Don't wait for AUX power well enable ACKs
85a603e64280 drm/i915/dg2: Skip shared DPLL handling
ee4554dd0f46 drm/i915/dg2: Add cdclk table and reference clock
bf4e9f961c54 drm/i915/dg2: Add fake PCH
0f78529c87f9 drm/i915/xehp: New engine context offsets
66471aa168d2 drm/i915/xehp: Handle new device context ID format
748de8c99157 drm/i915/selftests: Allow for larger engine counts
54b16faca000 drm/i915/gen12: Use fuse info to enable SFC
2024f48f8303 drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based
2e778d91bf0c drm/i915: Fork DG1 interrupt handler
af8335fc25c0 drm/i915/dg2: add DG2 platform info
35b61c43f3e6 drm/i915/xehpsdv: add initial XeHP SDV definitions
3c0d66813984 drm/i915: Add XE_HP initial definitions

_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Index of Archives]     [AMD Graphics]     [Linux USB Devel]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]

  Powered by Linux