> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
> Matt Roper
> Sent: Tuesday, July 13, 2021 8:16 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH v2 40/50] drm/i915/dg2: DG2 has fixed memory
> bandwidth
>
> DG2 doesn't have a SAGV or QGV points that determine memory bandwidth.
> Instead it has a constant amount of memory bandwidth available to display
> that does not need to be reduced based on the number of active planes.
>
> For simplicity, we'll just modify driver initialization to create a single dummy
> QGV point with the proper amount of memory bandwidth, rather than trying
> to query the pcode for this information.
>
> Bspec: 64631
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 24
> +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 0d5d52548925..f554c1974072 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -273,6 +273,26 @@ static int icl_get_bw_info(struct drm_i915_private
> *dev_priv, const struct intel
> return 0;
> }
>
> +static void dg2_get_bw_info(struct drm_i915_private *i915) {
> + struct intel_bw_info *bi = &i915->max_bw[0];
> +
> + /*
> + * DG2 doesn't have SAGV or QGV points, just a constant max
> bandwidth
> + * that doesn't depend on the number of planes enabled. Create a
> + * single dummy QGV point to reflect that. DG2-G10 platforms have
> a
> + * constant 50 GB/s bandwidth, whereas DG2-G11 platforms have 38
> GB/s.
> + */
> + bi->num_planes = 1;
> + bi->num_qgv_points = 1;
> + if (IS_DG2_G11(i915))
> + bi->deratedbw[0] = 38000;
> + else
> + bi->deratedbw[0] = 50000;
> +
> + i915->sagv_status = I915_SAGV_NOT_CONTROLLED; }
> +
> static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
> int num_planes, int qgv_point) { @@ -306,7
> +326,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
> + if (IS_DG2(dev_priv))
> + dg2_get_bw_info(dev_priv);
> + else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
> icl_get_bw_info(dev_priv, &adls_sa_info);
> else if (IS_ROCKETLAKE(dev_priv))
> icl_get_bw_info(dev_priv, &rkl_sa_info);
> --
> 2.25.4
>
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