On Fri, 2021-07-16 at 22:14 -0700, Matt Roper wrote: > DFR programming (which we enable as an optimization on gen11, but must > ensure is disabled on gen12) should be handled as a GT workaround rather > than clock gating initialization. This will ensure that the programming > of these registers is verified with our typical workaround checks. Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++ > drivers/gpu/drm/i915/intel_pm.c | 8 -------- > 2 files changed, 9 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 36d972492883..685c6115d380 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -965,6 +965,12 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > wa_write_or(wal, > SLICE_UNIT_LEVEL_CLKGATE, > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); > + > + /* > + * This is not a documented workaround, but rather an optimization > + * to reduce sampler power. > + */ > + wa_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); > } > > /* > @@ -998,6 +1004,9 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915, > > /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ > wa_14011060649(i915, wal); > + > + /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ > + wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); > } > > static void > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ef5304d3c2ec..8a84abfaa4b0 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7345,10 +7345,6 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv) > intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, > ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL); > > - /* This is not an Wa. Enable to reduce Sampler power */ > - intel_uncore_write(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN, > - intel_uncore_read(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE); > - > /*Wa_14010594013:icl, ehl */ > intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, > 0, CNL_DELAY_PMRSP); > @@ -7367,10 +7363,6 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) > intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) | > TGL_VRH_GATING_DIS); > > - /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ > - intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN, > - 0, DFR_DISABLE); > - > /* Wa_14013723622:tgl,rkl,dg1,adl-s */ > if (DISPLAY_VER(dev_priv) == 12) > intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY, _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
