On Tue, Apr 23, 2013 at 02:52:21PM -0300, Rodrigo Vivi wrote:
> Display register 46500h bit 23 must be set to 1b for the entire time that
> Frame Buffer Compression is enabled.
>
> v2: Ville suggested to enable it back when disabling fbc to avoid wasting
> power.
>
> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cb2d74c..bd2f64d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -871,6 +871,9 @@
> _HSW_PIPE_SLICE_CHICKEN_1_A, + \
> _HSW_PIPE_SLICE_CHICKEN_1_B)
>
> +#define HSW_CLKGATE_DISABLE_PART_1 0x46500
> +#define HSW_DPFC_GATING_DISABLE (1<<23)
> +
> /*
> * GPIO regs
> */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f81b25f..7e8caba 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -247,6 +247,11 @@ static void ironlake_disable_fbc(struct drm_device *dev)
> I915_WRITE(ILK_DSPCLK_GATE_D,
> ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
>
> + if(IS_HASWELL(dev))
> + /* WaFbcDisableDpfcClockGating */
> + I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
> + ~HSW_DPFC_GATING_DISABLE);
Should be '0' or maybe better do RMW instead in case someone has to
touch this register from somwhere else.
Same issue in IVB patch btw, just didn't spot it then.
> +
> DRM_DEBUG_KMS("disabled FBC\n");
> }
> }
> @@ -284,6 +289,8 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
> /* WaFbcAsynchFlipDisableFbcQueue */
> I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
> HSW_BYPASS_FBC_QUEUE);
> + /* WaFbcDisableDpfcClockGating */
> + I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, HSW_DPFC_GATING_DISABLE);
> }
>
> I915_WRITE(SNB_DPFC_CTL_SA,
> --
> 1.8.1.4
--
Ville Syrj?l?
Intel OTC
