On Tue, 2021-07-13 at 20:15 -0700, Matt Roper wrote:
> DG2 extends our DDB to four DBuf slices; pipes A+B only have access to
> the first two slices, whereas pipes C+D only have access to the second
> two.
>
> Confusingly, our bspec decided to switch from 1-based numbering
> of dbuf slices (S1, S2) to 0-based numbering (S0, S1, S2, S3) in
> Display13. At the moment we're using the 0-based number scheme for the
> DBUF_CTL_S() register addressing, but the 1-based number scheme in the
> actual slice assignment tables. We may want to consider switching the
> assignment over to 0-based numbering too at some point...
>
Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Bspec: 49255
> Bspec: 50057
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> .../drm/i915/display/intel_display_power.h | 4 +
> drivers/gpu/drm/i915/intel_pm.c | 120 +++++++++++++++++-
> 2 files changed, 123 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 22367b5cba96..ad788bbd727d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -392,6 +392,10 @@ intel_display_power_put_all_in_set(struct drm_i915_private *i915,
> intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask);
> }
>
> +/*
> + * FIXME: We should probably switch this to a 0-based scheme to be consistent
> + * with how we now name/number DBUF_CTL instances.
> + */
> enum dbuf_slice {
> DBUF_S1,
> DBUF_S2,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0cbb79452fcf..d7c7f061a26e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4584,6 +4584,117 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
> {}
> };
>
> +static const struct dbuf_slice_conf_entry dg2_allowed_dbufs[] = {
> + {
> + .active_pipes = BIT(PIPE_A),
> + .dbuf_mask = {
> + [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_B),
> + .dbuf_mask = {
> + [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
> + .dbuf_mask = {
> + [PIPE_A] = BIT(DBUF_S1),
> + [PIPE_B] = BIT(DBUF_S2),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_C),
> + .dbuf_mask = {
> + [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
> + .dbuf_mask = {
> + [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> + [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
> + .dbuf_mask = {
> + [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
> + [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .dbuf_mask = {
> + [PIPE_A] = BIT(DBUF_S1),
> + [PIPE_B] = BIT(DBUF_S2),
> + [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_D),
> + .dbuf_mask = {
> + [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
> + .dbuf_mask = {
> + [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> + [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
> + .dbuf_mask = {
> + [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
> + [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
> + .dbuf_mask = {
> + [PIPE_A] = BIT(DBUF_S1),
> + [PIPE_B] = BIT(DBUF_S2),
> + [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
> + .dbuf_mask = {
> + [PIPE_C] = BIT(DBUF_S3),
> + [PIPE_D] = BIT(DBUF_S4),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
> + .dbuf_mask = {
> + [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> + [PIPE_C] = BIT(DBUF_S3),
> + [PIPE_D] = BIT(DBUF_S4),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> + .dbuf_mask = {
> + [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
> + [PIPE_C] = BIT(DBUF_S3),
> + [PIPE_D] = BIT(DBUF_S4),
> + },
> + },
> + {
> + .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> + .dbuf_mask = {
> + [PIPE_A] = BIT(DBUF_S1),
> + [PIPE_B] = BIT(DBUF_S2),
> + [PIPE_C] = BIT(DBUF_S3),
> + [PIPE_D] = BIT(DBUF_S4),
> + },
> + },
> + {}
> +};
> +
> static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
> {
> .active_pipes = BIT(PIPE_A),
> @@ -4759,12 +4870,19 @@ static u32 adlp_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)
> return compute_dbuf_slices(pipe, active_pipes, adlp_allowed_dbufs);
> }
>
> +static u32 dg2_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)
> +{
> + return compute_dbuf_slices(pipe, active_pipes, dg2_allowed_dbufs);
> +}
> +
> static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> - if (IS_ALDERLAKE_P(dev_priv))
> + if (IS_DG2(dev_priv))
> + return dg2_compute_dbuf_slices(pipe, active_pipes);
> + else if (IS_ALDERLAKE_P(dev_priv))
> return adlp_compute_dbuf_slices(pipe, active_pipes);
> else if (DISPLAY_VER(dev_priv) == 12)
> return tgl_compute_dbuf_slices(pipe, active_pipes);
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