On Tue, 2021-07-13 at 20:15 -0700, Matt Roper wrote:
> On DG2 we're supposed to just wait 600us after programming the well
> before moving on; there won't be an ack from the hardware.
>
Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Bspec: 49296
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> .../gpu/drm/i915/display/intel_display_power.c | 16 ++++++++++++++++
> .../gpu/drm/i915/display/intel_display_power.h | 6 ++++++
> 2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index d92db471411e..04af987f3324 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -341,6 +341,17 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
> {
> const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> int pw_idx = power_well->desc->hsw.idx;
> + int enable_delay = power_well->desc->hsw.fixed_enable_delay;
> +
> + /*
> + * For some power wells we're not supposed to watch the status bit for
> + * an ack, but rather just wait a fixed amount of time and then
> + * proceed. This is only used on DG2.
> + */
> + if (IS_DG2(dev_priv) && enable_delay) {
> + usleep_range(enable_delay, 2 * enable_delay);
> + return;
> + }
>
> /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
> if (intel_de_wait_for_set(dev_priv, regs->driver,
> @@ -4828,6 +4839,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> + .hsw.fixed_enable_delay = 600,
> },
> },
> {
> @@ -4838,6 +4850,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> + .hsw.fixed_enable_delay = 600,
> },
> },
> {
> @@ -4848,6 +4861,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> + .hsw.fixed_enable_delay = 600,
> },
> },
> {
> @@ -4858,6 +4872,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
> + .hsw.fixed_enable_delay = 600,
> },
> },
> {
> @@ -4878,6 +4893,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
> {
> .hsw.regs = &icl_aux_power_well_regs,
> .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> + .hsw.fixed_enable_delay = 600,
> },
> },
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 4f0917df4375..22367b5cba96 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -223,6 +223,12 @@ struct i915_power_well_desc {
> u8 idx;
> /* Mask of pipes whose IRQ logic is backed by the pw */
> u8 irq_pipe_mask;
> + /*
> + * Instead of waiting for the status bit to ack enables,
> + * just wait a specific amount of time and then consider
> + * the well enabled.
> + */
> + u16 fixed_enable_delay;
> /* The pw is backing the VGA functionality */
> bool has_vga:1;
> bool has_fuses:1;
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