Hi Daniel, I'm feeling like I miss a ton of context here, so some maybe dumb questions/remarks below. Am Dienstag, dem 06.07.2021 um 12:12 +0200 schrieb Daniel Vetter: > There's only one exclusive slot, and we must not break the ordering. > > A better fix would be to us a dma_fence_chain or _array like e.g. > amdgpu now uses, but it probably makes sense to lift this into > dma-resv.c code as a proper concept, so that drivers don't have to > hack up their own solution each on their own. Hence go with the simple > fix for now. > > Another option is the fence import ioctl from Jason: > > https://lore.kernel.org/dri-devel/20210610210925.642582-7-jason@xxxxxxxxxxxxxx/ Sorry, but why is the fence import ioctl a alternative to the fix proposed in this patch? > > Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxxx> > Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > Cc: Russell King <linux+etnaviv@xxxxxxxxxxxxxxx> > Cc: Christian Gmeiner <christian.gmeiner@xxxxxxxxx> > Cc: etnaviv@xxxxxxxxxxxxxxxxxxxxx > --- > drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c > index 92478a50a580..5c4fed2b7c6a 100644 > --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c > +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c > @@ -178,18 +178,20 @@ static int submit_fence_sync(struct etnaviv_gem_submit *submit) > for (i = 0; i < submit->nr_bos; i++) { > struct etnaviv_gem_submit_bo *bo = &submit->bos[i]; > struct dma_resv *robj = bo->obj->base.resv; > + bool write = bo->flags & ETNA_SUBMIT_BO_WRITE; > > - if (!(bo->flags & ETNA_SUBMIT_BO_WRITE)) { > + if (!(write)) { No parenthesis around the write needed. > ret = dma_resv_reserve_shared(robj, 1); > if (ret) > return ret; > } > > - if (submit->flags & ETNA_SUBMIT_NO_IMPLICIT) > + /* exclusive fences must be ordered */ I feel like this comment isn't really helpful. It might tell you all you need to know if you just paged in all the context around dma_resv and the dependency graph, but it's not more than noise to me right now. I guess the comment should answer the question against what the exclusive fence we are going to add needs to be ordered and why it isn't safe to skip implicit sync in that case. Regards, Lucas > + if (submit->flags & ETNA_SUBMIT_NO_IMPLICIT && !write) > continue; > > ret = drm_sched_job_await_implicit(&submit->sched_job, &bo->obj->base, > - bo->flags & ETNA_SUBMIT_BO_WRITE); > + write); > if (ret) > return ret; > } _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
