Hi Imre, I applied this patch to today drm-tip and it applied cleanely. Could you please help with mergin it? Thanks Khaled On Fri, 2021-02-26 at 00:15 -0800, Almahallawy, Khaled wrote: > Source needs to write DPCD 103-106 after receiving a PHY request to > change > swing/pre-emphasis after reading DPCD 206-207. This is especially > needed if > there is a retimer between source and sink and the retimer implements > AUX_CH > interception scheme to manage DP PHY settings (e.g. adjusting > Swing/Pre-emphasis > equalization level) for DP output channel. If the source doesn't > write to > DPCD 103-106, the retimer may not output the requested swing/pre- > emphasis and > eventually we fail compliance. > > v2: Rebase and use crtc->lane_count (Imre) > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 2ec82a5c9f24..1ccf8602b3ef 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4471,6 +4471,9 @@ static void intel_dp_process_phy_request(struct > intel_dp *intel_dp, > > intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state); > > + drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, > + intel_dp->train_set, crtc_state->lane_count); > + > drm_dp_set_phy_test_pattern(&intel_dp->aux, data, > link_status[DP_DPCD_REV]); > } _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
